On Sat, Mar 8, 2014 at 7:50 PM, Ben Widawsky <ben@xxxxxxxxxxxx> wrote: > I've seen this too. Though I think the WARN does coincide with what the > docs state - it doesn't seem to match reality. So I totally agree this > is the right course. > > However, for my curiosity, Chris, can you elaborate on why you think it > doesn't make sense? Our current fifo code would be broken - we stall for the fifo entries to refill if the value drops below NUM_FIFO_ENTRIES_RESERVED. Hence if the register value is zero right after reset, something is terribly broken. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
