On Wed, Mar 05, 2014 at 02:40:58PM +0000, Damien Lespiau wrote: > On Wed, Mar 05, 2014 at 01:05:47PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote: > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > We have two names for the same register CHICKEN_PIPESL_1 and > > HSW_PIPE_SLICE_CHICKEN_1. Unify it to just one. > > > > Also rename the FBCQ disable bit to resemble the name we've > > given to a similar bit on earlier platforms. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Reviewed-by: Damien Lespiau <damien.lespiau@xxxxxxxxx> Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
