On Wed, Mar 05, 2014 at 01:05:47PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > We have two names for the same register CHICKEN_PIPESL_1 and > HSW_PIPE_SLICE_CHICKEN_1. Unify it to just one. > > Also rename the FBCQ disable bit to resemble the name we've > given to a similar bit on earlier platforms. > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Reviewed-by: Damien Lespiau <damien.lespiau@xxxxxxxxx> -- Damien > --- > drivers/gpu/drm/i915/i915_reg.h | 10 ++-------- > drivers/gpu/drm/i915/intel_pm.c | 8 ++++---- > 2 files changed, 6 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e313035..ad3151a 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1126,13 +1126,6 @@ > #define FBC_REND_NUKE (1<<2) > #define FBC_REND_CACHE_CLEAN (1<<1) > > -#define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0 > -#define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4 > -#define HSW_BYPASS_FBC_QUEUE (1<<22) > -#define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \ > - _HSW_PIPE_SLICE_CHICKEN_1_A, + \ > - _HSW_PIPE_SLICE_CHICKEN_1_B) > - > /* > * GPIO regs > */ > @@ -4145,7 +4138,8 @@ > > #define _CHICKEN_PIPESL_1_A 0x420b0 > #define _CHICKEN_PIPESL_1_B 0x420b4 > -#define DPRS_MASK_VBLANK_SRD (1 << 0) > +#define HSW_FBCQ_DIS (1 << 22) > +#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) > #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) > > #define DISP_ARB_CTL 0x45000 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 3411ad7..7a693e9 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -299,9 +299,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc) > ILK_FBCQ_DIS); > } else { > /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ > - I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), > - I915_READ(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe)) | > - HSW_BYPASS_FBC_QUEUE); > + I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe), > + I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) | > + HSW_FBCQ_DIS); > } > > I915_WRITE(SNB_DPFC_CTL_SA, > @@ -4836,7 +4836,7 @@ static void gen8_init_clock_gating(struct drm_device *dev) > for_each_pipe(i) { > I915_WRITE(CHICKEN_PIPESL_1(i), > I915_READ(CHICKEN_PIPESL_1(i)) | > - DPRS_MASK_VBLANK_SRD); > + BDW_DPRS_MASK_VBLANK_SRD); > } > > /* Use Force Non-Coherent whenever executing a 3D context. This is a > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx