On Wed, Mar 05, 2014 at 06:08:19PM +0200, Mika Kuoppala wrote: > There should not be a case where fifo count is other > than zero after a successful reset. Always set > count to zero, but be paranoid enough to warn. > > v2: rebased > > Suggested-by: Ben Widawsky <ben@xxxxxxxxxxxx> > Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_uncore.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 00320fd..79eaba8 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -988,9 +988,10 @@ static int gen6_do_reset(struct drm_device *dev) > dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine); > > if (IS_GEN6(dev) || IS_GEN7(dev)) > - dev_priv->uncore.fifo_count = > - __raw_i915_read32(dev_priv, GTFIFOCTL) & > - GT_FIFO_FREE_ENTRIES_MASK; > + WARN_ON((__raw_i915_read32(dev_priv, GTFIFOCTL) & > + GT_FIFO_FREE_ENTRIES_MASK) != 0); > + > + dev_priv->uncore.fifo_count = 0; > > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); > return ret; Can you please add the following to the commit message: "The GT FIFO is bypassed when not in RC6 from both IA and SA. As we've just reset the GPU and not yet enabled RC6, there is no way the FIFO can be anything but 0. If it is non-zero, it's a HW bug, and we can try to carry on by faking it. It should be noted that RC6 is highly unlikely to work properly if this WARN fires, however the system should continue on just fine." With that: Reviewed-by: Ben Widawsky <ben@xxxxxxxxxxxx> -- Ben Widawsky, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
