On Mon, 03 Mar 2014, Daniel Vetter <daniel.vetter@xxxxxxxx> wrote: > ... it's this time of the year again. Originally we've frobbed this to > fix up some regressions, but maybe our DP code improved sufficiently > now that we can dare to do again what the spec recommends. > > This reverts > > commit 2514bc510d0c3aadcc5204056bb440fa36845147 > Author: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> > Date: Thu Jun 21 15:13:50 2012 -0700 > > drm/i915: prefer wide & slow to fast & narrow in DP configs > > I'm pretty sure I'll regret this patch, but otoh I expect we won't > make progress here without poking the devil occasionally. Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx> I agree we should bite the bullet and do this. This is what the DP specs tell us to do. I'm pretty sure there will be regressions, but I'm also starting to believe there's a greater number of machines that are currently either broken beyond repair or papered over with some hacks than the number that will regress. We should just dig into them and fix them instead of burying our heads in the sand. BR, Jani. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73694 > Cc: peter@xxxxxxxxxxx > Cc: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> > Tested-by: Itai BEN YAACOV <candeb@xxxxxxx> > Tested-by: David En <d.engraf@xxxxxxxx> > Reported-and-Tested-by: Marcus Bergner <marcusbergner@xxxxxxxxx> > Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx> > --- > drivers/gpu/drm/i915/intel_dp.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 1ac4b11765c7..e50aadfc2184 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -909,8 +909,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, > mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, > bpp); > > - for (clock = 0; clock <= max_clock; clock++) { > - for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { > + for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { > + for (clock = 0; clock <= max_clock; clock++) { > link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); > link_avail = intel_dp_max_data_rate(link_clock, > lane_count); > -- > 1.8.5.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
