2014-02-27 9:23 GMT-03:00 <ville.syrjala@xxxxxxxxxxxxxxx>: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > If we need precisely N lanes to satisfy the FDI bandwidth requirement, > the code would still claim that we need N+1 lanes. Use DIV_ROUND_UP() > to get a more accurate answer. > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_display.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index a366e91..4702858 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6149,7 +6149,7 @@ int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) > * is 2.5%; use 5% for safety's sake. > */ > u32 bps = target_clock * bpp * 21 / 20; > - return bps / (link_bw * 8) + 1; > + return DIV_ROUND_UP(bps, link_bw * 8); > } > > static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
