From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> I just set out to fix [1], but I ended up massaging the FDI and DDI code a bit more than I initially intended. The SPLL sharing part is untested due to the PLL sharing and selection being hardcoded to the output type. So I would've had to massage the code even more to get it to use SPLL for non FDI outputs. It would be nice to make the code eventually more like the PCH PLL sharing code so it isn't so strictly tied in with the output type. I was thinking each output type should just have some kind of priority list of possible PLLs, and the PLL sharing code itself should be entirely oblivious about the output type. But that's something for the future... [1] https://bugs.freedesktop.org/show_bug.cgi?id=74955 Ville Syrjälä (5): drm/i915: Fix DDI port_clock for VGA output drm/i915: Change intel_fdi_link_freq() to 10kHz drm/i915: Use DIV_ROUND_UP() when calculating number of required FDI lanes drm/i915: Use port_clock for FDI frequency on DDI drm/i915: Add SPLL sharing support for DDI drivers/gpu/drm/i915/intel_crt.c | 4 ++++ drivers/gpu/drm/i915/intel_ddi.c | 45 +++++++++++++++++++++++++++++++----- drivers/gpu/drm/i915/intel_display.c | 29 +++++++++++------------ 3 files changed, 57 insertions(+), 21 deletions(-) -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
