Hi
2014-02-27 9:23 GMT-03:00 <ville.syrjala@xxxxxxxxxxxxxxx>:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Write some theoretical SPLL sharing support for DDI. Currently that will
> never happens since we never use SPLL for anything but FDI. But having
> the code there makes it easier if we ever want to do it, and it might
> excercise the PLL sharing code a bit more.
One thing is that if we ever want to use SSC on eDP/DP/HDMI, we will
want to use either SPLL or WRPLL instead of LCPLL. I always wanted to
implement this, and recently I saw a bug that made me think about it
again.
So instead of this patch, why don't you write support to use SSC when
requested? We could do this through some i915.use_ssc command line
option that would just try to force SSC on everything, or maybe a
"debug connector property", or debugfs, or anything you might want.
With this, you would be able to actually test your patches, and we'd
have a useful feature.
If you disagree, please just say "no" and then I'll go back to review
this patch :)
Thanks,
Paulo
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 45 ++++++++++++++++++++++++++++++++++------
> 1 file changed, 39 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 2643d3b..1dbe3e4 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -870,16 +870,35 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
> }
>
> } else if (type == INTEL_OUTPUT_ANALOG) {
> - if (plls->spll_refcount == 0) {
> + uint32_t val = SPLL_PLL_ENABLE | SPLL_PLL_SSC;
> +
> + switch (clock / 2) {
> + case 81000:
> + val |= SPLL_PLL_FREQ_810MHz;
> + break;
> + case 135000:
> + val |= SPLL_PLL_FREQ_1350MHz;
> + break;
> + case 270000:
> + val |= SPLL_PLL_FREQ_2700MHz;
> + break;
> + default:
> + DRM_ERROR("SPLL frequency %d kHz unsupported\n", clock / 2);
> + return false;
> + }
> +
> + if (val == I915_READ(SPLL_CTL)) {
> + DRM_DEBUG_KMS("Reusing SPLL on pipe %c\n",
> + pipe_name(pipe));
> + } else if (plls->spll_refcount == 0) {
> DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
> pipe_name(pipe));
> - plls->spll_refcount++;
> - intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
> } else {
> DRM_ERROR("SPLL already in use\n");
> return false;
> }
> -
> + plls->spll_refcount++;
> + intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
> } else {
> WARN(1, "Invalid DDI encoder type %d\n", type);
> return false;
> @@ -921,8 +940,22 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc)
> pll_name = "SPLL";
> reg = SPLL_CTL;
> refcount = plls->spll_refcount;
> - new_val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz |
> - SPLL_PLL_SSC;
> + new_val = SPLL_PLL_ENABLE | SPLL_PLL_SSC;
> +
> + switch (clock / 2) {
> + case 81000:
> + new_val |= SPLL_PLL_FREQ_810MHz;
> + break;
> + case 135000:
> + new_val |= SPLL_PLL_FREQ_1350MHz;
> + break;
> + case 270000:
> + new_val |= SPLL_PLL_FREQ_2700MHz;
> + break;
> + default:
> + WARN(1, "Bad SPLL frequency %d\n", clock / 2);
> + return;
> + }
> break;
>
> case PORT_CLK_SEL_WRPLL1:
> --
> 1.8.3.2
>
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--
Paulo Zanoni
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