On 02/04/2014 09:59 PM, ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > So I accidentally looked at gen6_init_clock_gating() and noticed a few > weird things that should have gotten cleaned up years ago. So I did that. > > While doing that I also noticed the WIZ hashing bits, and the fact that > we weren't following the BSpec recommendation. After doing a few tests > on IVB and HSW it looks 16x4 is in fact the best option, 8x4 was second > best and 8x8 (our current default for !SNB) was the worst. I didn't see > much (if any) difference w/o MSAA, but w/ MSAA 4x there was some change. > I used xonotic as my benchmark. > > Ville Syrjälä (7): > drm/i915: Fix SNB GT_MODE register setup > drm/i915: Assume we implement > WaStripsFansDisableFastClipPerformanceFix:snb > drm/i915: There's no need to mask all 3D_CHICKEN bits on SNB > drm/i915: Disable SF pipelined attribute fetch for SNB > drm/i915: Change IVB WIZ hashing mode to 16x4 > drm/i915: Change HSW WIZ hashing mode to 16x4 > drm/i915: Change BDW WIZ hashing mode to 16x4 > > drivers/gpu/drm/i915/i915_reg.h | 10 +++++++-- > drivers/gpu/drm/i915/intel_pm.c | 47 ++++++++++++++++++++++++++++++++++------- > 2 files changed, 47 insertions(+), 10 deletions(-) For everything except 4/7, which was reviewed by Ken: Reviewed-by: Antti Koskipää <antti.koskipaa@xxxxxxxxxxxxxxx> -- - Antti _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
