On Tue, Feb 11, 2014 at 03:55:50PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > According to BSpec the entire MI_DISPLAY_FLIP packet must be contained > in a single cacheline. Make sure that happens. > > v2: Use intel_ring_begin_cacheline_safe() Ugh, no. Let's not make intel_ring_begin() any more complicated and just introduce a function to align the current head in the ringbuffer to a cacheline. Especially with such an interface that is hard to get right. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
