From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> According to BSpec the entire MI_DISPLAY_FLIP packet must be contained in a single cacheline. Make sure that happens. v2: Use intel_ring_begin_cacheline_safe() Cc: Bjoern C <lkml@xxxxxxxxxxxx> Cc: Alexandru DAMIAN <alexandru.damian@xxxxxxxxx> Cc: Enrico Tagliavini <enrico.tagliavini@xxxxxxxxx> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74053 Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/intel_display.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0c25310..361a9a9 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8579,7 +8579,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev, struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_ring_buffer *ring; uint32_t plane_bit = 0; - int len, ret; + int extra, len = 0, ret; ring = obj->ring; if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) @@ -8605,11 +8605,14 @@ static int intel_gen7_queue_flip(struct drm_device *dev, goto err_unpin; } - len = 4; if (ring->id == RCS) len += 6; - ret = intel_ring_begin(ring, len); + /* + * BSpec MI_DISPLAY_FLIP for IVB: + * "The full packet must be contained within the same cache line." + */ + ret = intel_ring_begin_cacheline_safe(ring, len, 4, len + 4, &extra); if (ret) goto err_unpin; @@ -8634,6 +8637,9 @@ static int intel_gen7_queue_flip(struct drm_device *dev, intel_ring_emit(ring, ring->scratch.gtt_offset + 256); } + while (extra--) + intel_ring_emit(ring, MI_NOOP); + intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
