Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
On Wed, Jan 22, 2014 at 5:33 PM, <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> I can't see WaDisableDopClockGating listed for IVB in W/A database.
>
> Also I'm not quite sure we were even disabling the right thing. Register
> 0x9424 has one DOP clock gating disable bit, amd 0xe4f4/0xf4f4 appears
> to have another one, but I don't actually know which is the one were
> suposed to frob. This question is more relevant for VLV where this
> workaround is still being applied via register 0xe4f4. Maybe it should
> actually use 0x9424 instead.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 12 ------------
> 1 file changed, 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ff8e72e..d95a3a6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4826,18 +4826,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
> GEN7_WA_L3_CHICKEN_MODE);
>
> - /* WaDisableDopClockGating:ivb */
> - if (IS_IVB_GT1(dev))
> - I915_WRITE(GEN7_ROW_CHICKEN2,
> - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> - else {
> - /* must write both registers */
> - I915_WRITE(GEN7_ROW_CHICKEN2,
> - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> - I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
> - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> - }
> -
> /* WaForceL3Serialization:ivb */
> I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
> --
> 1.8.3.2
>
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--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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