On Fri, Jan 24, 2014 at 12:53 PM, Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > On Thu, Jan 23, 2014 at 05:19:53PM -0200, Rodrigo Vivi wrote: > <snip> >> index 76126e0..f5501ab 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -1969,6 +1969,40 @@ >> #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) >> #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) >> >> +/* VLV eDP PSR registers */ >> +#define VLV_EDP_PSR_CTL (VLV_DISPLAY_BASE + 0x60090) > > VLV has per-pipe PSR registers. The ones you have here are just for > pipe A. Seems like some rework is needed to make it work on either > pipe. Yes, but since I don't have any hw with two eDPs here I decided to let the limitation we had for HSW, PSR only on pipe A. In my point of view we could go ahead with this one eDP scenario and implement psr on pipe b support later. > > > -- > Ville Syrjälä > Intel OTC -- Rodrigo Vivi Blog: http://blog.vivi.eng.br _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
