Turns out it'd be nice to change some device information at run-time or
simply have some code to fill in the info struct instead of having to
declare the values in 30+ structures.
What prompted this change is handling fused out display/pipe and
tweaking num_pipes at run-time, but I'm quite sure we'll find other
flags/limits to stick into dev_priv->info.
Most of the changes were done with two sed commands:
sed -i -e 's/dev_priv->info->/dev_priv->info./g' drivers/gpu/drm/i915/*[ch]
sed -i -e 's/to_i915(\(.*\))->info->/to_i915(\1)->info./g' drivers/gpu/drm/i915/*[ch]
with a few tweaks to make it all work:
- Change the field definition in struct drm_i915_private
- adjust i915_dump_device_info()
- adjust i915_driver_load()
- adjust i915_debugfs.c:i915_capabilities() that needed a pointer to
dev_priv->info.
v2: cast the info pointer returned by INTEL_INFO() to be const to catch
uses that would modify the structure post-initialization.
(Ville Syrjälä)
v3: Rebase on to of the INTEL_INFO() removal
Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> (for v2)
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> (for v2)
Signed-off-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 ++--
drivers/gpu/drm/i915/i915_dma.c | 45 ++++--
drivers/gpu/drm/i915/i915_drv.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 82 +++++------
drivers/gpu/drm/i915/i915_gem.c | 26 ++--
drivers/gpu/drm/i915/i915_gem_context.c | 10 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 20 +--
drivers/gpu/drm/i915/i915_gem_gtt.c | 18 +--
drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
drivers/gpu/drm/i915/i915_gem_tiling.c | 12 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 32 ++--
drivers/gpu/drm/i915/i915_irq.c | 50 +++----
drivers/gpu/drm/i915/i915_reg.h | 228 ++++++++++++++---------------
drivers/gpu/drm/i915/i915_suspend.c | 14 +-
drivers/gpu/drm/i915/i915_sysfs.c | 4 +-
drivers/gpu/drm/i915/i915_ums.c | 24 +--
drivers/gpu/drm/i915/intel_bios.c | 2 +-
drivers/gpu/drm/i915/intel_crt.c | 6 +-
drivers/gpu/drm/i915/intel_display.c | 134 ++++++++---------
drivers/gpu/drm/i915/intel_fbdev.c | 4 +-
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/intel_i2c.c | 2 +-
drivers/gpu/drm/i915/intel_lvds.c | 8 +-
drivers/gpu/drm/i915/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/intel_panel.c | 10 +-
drivers/gpu/drm/i915/intel_pm.c | 72 ++++-----
drivers/gpu/drm/i915/intel_ringbuffer.c | 54 +++----
drivers/gpu/drm/i915/intel_sdvo.c | 10 +-
drivers/gpu/drm/i915/intel_sprite.c | 4 +-
drivers/gpu/drm/i915/intel_tv.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 10 +-
31 files changed, 468 insertions(+), 453 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index db8f381..91fb09d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -81,7 +81,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
- const struct intel_device_info *info = to_i915(dev)->info;
+ const struct intel_device_info *info = &to_i915(dev)->info;
seq_printf(m, "gen: %d\n", info->gen);
seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
@@ -601,7 +601,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
return ret;
intel_runtime_pm_get(dev_priv);
- if (dev_priv->info->gen >= 8) {
+ if (dev_priv->info.gen >= 8) {
int i;
seq_printf(m, "Master Interrupt Control:\t%08x\n",
I915_READ(GEN8_MASTER_IRQ));
@@ -719,7 +719,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
seq_printf(m, "Interrupts received: %d\n",
atomic_read(&dev_priv->irq_received));
for_each_ring(ring, dev_priv, i) {
- if (dev_priv->info->gen >= 6) {
+ if (dev_priv->info.gen >= 6) {
seq_printf(m,
"Graphics Interrupt mask (%s): %08x\n",
ring->name, I915_READ_IMR(ring));
@@ -1667,7 +1667,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
I915_READ16(C0DRB3));
seq_printf(m, "C1DRB3 = 0x%04x\n",
I915_READ16(C1DRB3));
- } else if (dev_priv->info->gen >= 6) {
+ } else if (dev_priv->info.gen >= 6) {
seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
I915_READ(MAD_DIMM_C0));
seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
@@ -1734,12 +1734,12 @@ static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
struct drm_file *file;
int i;
- if (dev_priv->info->gen == 6)
+ if (dev_priv->info.gen == 6)
seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
for_each_ring(ring, dev_priv, i) {
seq_printf(m, "%s\n", ring->name);
- if (dev_priv->info->gen == 7)
+ if (dev_priv->info.gen == 7)
seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
@@ -1779,9 +1779,9 @@ static int i915_ppgtt_info(struct seq_file *m, void *data)
return ret;
intel_runtime_pm_get(dev_priv);
- if (dev_priv->info->gen >= 8)
+ if (dev_priv->info.gen >= 8)
gen8_ppgtt_info(m, dev);
- else if (dev_priv->info->gen >= 6)
+ else if (dev_priv->info.gen >= 6)
gen6_ppgtt_info(m, dev);
intel_runtime_pm_put(dev_priv);
@@ -1884,7 +1884,7 @@ static int i915_energy_uJ(struct seq_file *m, void *data)
u64 power;
u32 units;
- if (dev_priv->info->gen < 6)
+ if (dev_priv->info.gen < 6)
return -ENODEV;
rdmsrl(MSR_RAPL_POWER_UNIT, power);
@@ -2004,7 +2004,7 @@ static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
struct drm_i915_private *dev_priv = info->dev->dev_private;
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
- if (info->pipe >= dev_priv->info->num_pipes)
+ if (info->pipe >= dev_priv->info.num_pipes)
return -ENODEV;
spin_lock_irq(&pipe_crc->lock);
@@ -2509,7 +2509,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
if (IS_GEN2(dev))
ret = i8xx_pipe_crc_ctl_reg(&source, &val);
- else if (dev_priv->info->gen < 5)
+ else if (dev_priv->info.gen < 5)
ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
else if (IS_VALLEYVIEW(dev))
ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
@@ -3133,7 +3133,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
struct drm_device *dev = inode->i_private;
struct drm_i915_private *dev_priv = dev->dev_private;
- if (dev_priv->info->gen < 6)
+ if (dev_priv->info.gen < 6)
return 0;
intel_runtime_pm_get(dev_priv);
@@ -3147,7 +3147,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file)
struct drm_device *dev = inode->i_private;
struct drm_i915_private *dev_priv = dev->dev_private;
- if (dev_priv->info->gen < 6)
+ if (dev_priv->info.gen < 6)
return 0;
gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 188e340..2b10e41 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -107,7 +107,7 @@ static void i915_write_hws_pga(struct drm_device *dev)
u32 addr;
addr = dev_priv->status_page_dmah->busaddr;
- if (dev_priv->info->gen >= 4)
+ if (dev_priv->info.gen >= 4)
addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
I915_WRITE(HWS_PGA, addr);
}
@@ -399,7 +399,7 @@ i915_emit_box(struct drm_device *dev,
return -EINVAL;
}
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
ret = BEGIN_LP_RING(4);
if (ret)
return ret;
@@ -512,7 +512,7 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev,
if (ret)
return ret;
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
OUT_RING(batch->start);
} else {
@@ -975,7 +975,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = 1;
break;
case I915_PARAM_HAS_EXEC_CONSTANTS:
- value = dev_priv->info->gen >= 4;
+ value = dev_priv->info.gen >= 4;
break;
case I915_PARAM_HAS_RELAXED_DELTA:
value = 1;
@@ -1133,12 +1133,12 @@ static int
intel_alloc_mchbar_resource(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = dev->dev_private;
- int reg = dev_priv->info->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+ int reg = dev_priv->info.gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
u32 temp_lo, temp_hi = 0;
u64 mchbar_addr;
int ret;
- if (dev_priv->info->gen >= 4)
+ if (dev_priv->info.gen >= 4)
pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
@@ -1165,7 +1165,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
return ret;
}
- if (dev_priv->info->gen >= 4)
+ if (dev_priv->info.gen >= 4)
pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
upper_32_bits(dev_priv->mch_res.start));
@@ -1179,7 +1179,7 @@ static void
intel_setup_mchbar(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = dev->dev_private;
- int mchbar_reg = dev_priv->info->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+ int mchbar_reg = dev_priv->info.gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
u32 temp;
bool enabled;
@@ -1216,7 +1216,7 @@ static void
intel_teardown_mchbar(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = dev->dev_private;
- int mchbar_reg = dev_priv->info->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+ int mchbar_reg = dev_priv->info.gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
u32 temp;
if (dev_priv->mchbar_need_disable) {
@@ -1338,7 +1338,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
/* Always safe in the mode setting case. */
/* FIXME: do pre/post-mode set stuff in core KMS code */
dev->vblank_disable_allowed = true;
- if (dev_priv->info->num_pipes == 0) {
+ if (dev_priv->info.num_pipes == 0) {
intel_display_power_put(dev, POWER_DOMAIN_VGA);
return 0;
}
@@ -1442,7 +1442,7 @@ static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
static void i915_dump_device_info(struct drm_i915_private *dev_priv)
{
- const struct intel_device_info *info = dev_priv->info;
+ const struct intel_device_info *info = &dev_priv->info;
#define PRINT_S(name) "%s"
#define SEP_EMPTY
@@ -1459,6 +1459,20 @@ static void i915_dump_device_info(struct drm_i915_private *dev_priv)
#undef SEP_COMMA
}
+static void
+intel_device_info_init(struct drm_i915_private *dev_priv,
+ const struct intel_device_info *start_info)
+{
+ struct intel_device_info *info;
+
+ /*
+ * dev_priv->info is const for the rest of the driver but we make
+ * an exception here to copy the initial configuration.
+ */
+ info = (struct intel_device_info *)&dev_priv->info;
+ memcpy(info, start_info, sizeof(*info));
+}
+
/**
* i915_driver_load - setup chip and create an initial config
* @dev: DRM device
@@ -1496,7 +1510,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
dev->dev_private = (void *)dev_priv;
dev_priv->dev = dev;
- dev_priv->info = info;
+
+ intel_device_info_init(dev_priv, info);
spin_lock_init(&dev_priv->irq_lock);
spin_lock_init(&dev_priv->gpu_error.lock);
@@ -1639,8 +1654,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
if (IS_VALLEYVIEW(dev))
dev_priv->num_plane = 2;
- if (dev_priv->info->num_pipes) {
- ret = drm_vblank_init(dev, dev_priv->info->num_pipes);
+ if (dev_priv->info.num_pipes) {
+ ret = drm_vblank_init(dev, dev_priv->info.num_pipes);
if (ret)
goto out_gem_unload;
}
@@ -1660,7 +1675,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
i915_setup_sysfs(dev);
- if (dev_priv->info->num_pipes) {
+ if (dev_priv->info.num_pipes) {
/* Must be done after probing outputs */
intel_opregion_init(dev);
acpi_video_register();
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9134140..db43df6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -411,7 +411,7 @@ void intel_detect_pch(struct drm_device *dev)
/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
* (which really amounts to a PCH but no South Display).
*/
- if (dev_priv->info->num_pipes == 0) {
+ if (dev_priv->info.num_pipes == 0) {
dev_priv->pch_type = PCH_NOP;
return;
}
@@ -482,7 +482,7 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- if (dev_priv->info->gen < 6)
+ if (dev_priv->info.gen < 6)
return false;
/* Until we get further testing... */
@@ -496,7 +496,7 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
#ifdef CONFIG_INTEL_IOMMU
/* Enable semaphores on SNB when IO remapping is off */
- if (dev_priv->info->gen == 6 && intel_iommu_gfx_mapped)
+ if (dev_priv->info.gen == 6 && intel_iommu_gfx_mapped)
return false;
#endif
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 54ee3a8..9a6bd68 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -157,7 +157,7 @@ enum hpd_pin {
I915_GEM_DOMAIN_VERTEX)
#define for_each_pipe(p) \
- for ((p) = 0; (p) < to_i915(dev)->info->num_pipes; (p)++)
+ for ((p) = 0; (p) < to_i915(dev)->info.num_pipes; (p)++)
#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
@@ -1361,7 +1361,7 @@ typedef struct drm_i915_private {
struct drm_device *dev;
struct kmem_cache *slab;
- const struct intel_device_info *info;
+ const struct intel_device_info info;
int relative_constants_mode;
@@ -1774,32 +1774,32 @@ struct drm_i915_file_private {
#define IS_I830(dev) ((dev)->pdev->device == 0x3577)
#define IS_845G(dev) ((dev)->pdev->device == 0x2562)
-#define IS_I85X(dev) (to_i915(dev)->info->is_i85x)
+#define IS_I85X(dev) (to_i915(dev)->info.is_i85x)
#define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
-#define IS_I915G(dev) (to_i915(dev)->info->is_i915g)
+#define IS_I915G(dev) (to_i915(dev)->info.is_i915g)
#define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
#define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
-#define IS_I945GM(dev) (to_i915(dev)->info->is_i945gm)
-#define IS_BROADWATER(dev) (to_i915(dev)->info->is_broadwater)
-#define IS_CRESTLINE(dev) (to_i915(dev)->info->is_crestline)
+#define IS_I945GM(dev) (to_i915(dev)->info.is_i945gm)
+#define IS_BROADWATER(dev) (to_i915(dev)->info.is_broadwater)
+#define IS_CRESTLINE(dev) (to_i915(dev)->info.is_crestline)
#define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
-#define IS_G4X(dev) (to_i915(dev)->info->is_g4x)
+#define IS_G4X(dev) (to_i915(dev)->info.is_g4x)
#define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
#define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
-#define IS_PINEVIEW(dev) (to_i915(dev)->info->is_pineview)
-#define IS_G33(dev) (to_i915(dev)->info->is_g33)
+#define IS_PINEVIEW(dev) (to_i915(dev)->info.is_pineview)
+#define IS_G33(dev) (to_i915(dev)->info.is_g33)
#define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
-#define IS_IVYBRIDGE(dev) (to_i915(dev)->info->is_ivybridge)
+#define IS_IVYBRIDGE(dev) (to_i915(dev)->info.is_ivybridge)
#define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
(dev)->pdev->device == 0x0152 || \
(dev)->pdev->device == 0x015a)
#define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
(dev)->pdev->device == 0x0106 || \
(dev)->pdev->device == 0x010A)
-#define IS_VALLEYVIEW(dev) (to_i915(dev)->info->is_valleyview)
-#define IS_HASWELL(dev) (to_i915(dev)->info->is_haswell)
-#define IS_BROADWELL(dev) (to_i915(dev)->info->gen == 8)
-#define IS_MOBILE(dev) (to_i915(dev)->info->is_mobile)
+#define IS_VALLEYVIEW(dev) (to_i915(dev)->info.is_valleyview)
+#define IS_HASWELL(dev) (to_i915(dev)->info.is_haswell)
+#define IS_BROADWELL(dev) (to_i915(dev)->info.gen == 8)
+#define IS_MOBILE(dev) (to_i915(dev)->info.is_mobile)
#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
((dev)->pdev->device & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
@@ -1819,33 +1819,33 @@ struct drm_i915_file_private {
* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
* chips, etc.).
*/
-#define IS_GEN2(dev) (to_i915(dev)->info->gen == 2)
-#define IS_GEN3(dev) (to_i915(dev)->info->gen == 3)
-#define IS_GEN4(dev) (to_i915(dev)->info->gen == 4)
-#define IS_GEN5(dev) (to_i915(dev)->info->gen == 5)
-#define IS_GEN6(dev) (to_i915(dev)->info->gen == 6)
-#define IS_GEN7(dev) (to_i915(dev)->info->gen == 7)
-#define IS_GEN8(dev) (to_i915(dev)->info->gen == 8)
+#define IS_GEN2(dev) (to_i915(dev)->info.gen == 2)
+#define IS_GEN3(dev) (to_i915(dev)->info.gen == 3)
+#define IS_GEN4(dev) (to_i915(dev)->info.gen == 4)
+#define IS_GEN5(dev) (to_i915(dev)->info.gen == 5)
+#define IS_GEN6(dev) (to_i915(dev)->info.gen == 6)
+#define IS_GEN7(dev) (to_i915(dev)->info.gen == 7)
+#define IS_GEN8(dev) (to_i915(dev)->info.gen == 8)
#define RENDER_RING (1<<RCS)
#define BSD_RING (1<<VCS)
#define BLT_RING (1<<BCS)
#define VEBOX_RING (1<<VECS)
-#define HAS_BSD(dev) (to_i915(dev)->info->ring_mask & BSD_RING)
-#define HAS_BLT(dev) (to_i915(dev)->info->ring_mask & BLT_RING)
-#define HAS_VEBOX(dev) (to_i915(dev)->info->ring_mask & VEBOX_RING)
-#define HAS_LLC(dev) (to_i915(dev)->info->has_llc)
+#define HAS_BSD(dev) (to_i915(dev)->info.ring_mask & BSD_RING)
+#define HAS_BLT(dev) (to_i915(dev)->info.ring_mask & BLT_RING)
+#define HAS_VEBOX(dev) (to_i915(dev)->info.ring_mask & VEBOX_RING)
+#define HAS_LLC(dev) (to_i915(dev)->info.has_llc)
#define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
-#define I915_NEED_GFX_HWS(dev) (to_i915(dev)->info->need_gfx_hws)
+#define I915_NEED_GFX_HWS(dev) (to_i915(dev)->info.need_gfx_hws)
-#define HAS_HW_CONTEXTS(dev) (to_i915(dev)->info->gen >= 6)
-#define HAS_ALIASING_PPGTT(dev) (to_i915(dev)->info->gen >= 6 && !IS_VALLEYVIEW(dev))
-#define HAS_PPGTT(dev) (to_i915(dev)->info->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_BROADWELL(dev))
+#define HAS_HW_CONTEXTS(dev) (to_i915(dev)->info.gen >= 6)
+#define HAS_ALIASING_PPGTT(dev) (to_i915(dev)->info.gen >= 6 && !IS_VALLEYVIEW(dev))
+#define HAS_PPGTT(dev) (to_i915(dev)->info.gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_BROADWELL(dev))
#define USES_ALIASING_PPGTT(dev) intel_enable_ppgtt(dev, false)
#define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
-#define HAS_OVERLAY(dev) (to_i915(dev)->info->has_overlay)
-#define OVERLAY_NEEDS_PHYSICAL(dev) (to_i915(dev)->info->overlay_needs_physical)
+#define HAS_OVERLAY(dev) (to_i915(dev)->info.has_overlay)
+#define OVERLAY_NEEDS_PHYSICAL(dev) (to_i915(dev)->info.overlay_needs_physical)
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
@@ -1858,17 +1858,17 @@ struct drm_i915_file_private {
#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
-#define SUPPORTS_TV(dev) (to_i915(dev)->info->supports_tv)
-#define I915_HAS_HOTPLUG(dev) (to_i915(dev)->info->has_hotplug)
+#define SUPPORTS_TV(dev) (to_i915(dev)->info.supports_tv)
+#define I915_HAS_HOTPLUG(dev) (to_i915(dev)->info.has_hotplug)
-#define HAS_FW_BLC(dev) (to_i915(dev)->info->gen > 2)
-#define HAS_PIPE_CXSR(dev) (to_i915(dev)->info->has_pipe_cxsr)
-#define I915_HAS_FBC(dev) (to_i915(dev)->info->has_fbc)
+#define HAS_FW_BLC(dev) (to_i915(dev)->info.gen > 2)
+#define HAS_PIPE_CXSR(dev) (to_i915(dev)->info.has_pipe_cxsr)
+#define I915_HAS_FBC(dev) (to_i915(dev)->info.has_fbc)
#define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
-#define HAS_DDI(dev) (to_i915(dev)->info->has_ddi)
-#define HAS_FPGA_DBG_UNCLAIMED(dev) (to_i915(dev)->info->has_fpga_dbg)
+#define HAS_DDI(dev) (to_i915(dev)->info.has_ddi)
+#define HAS_FPGA_DBG_UNCLAIMED(dev) (to_i915(dev)->info.has_fpga_dbg)
#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
#define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
#define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev))
@@ -2296,7 +2296,7 @@ void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
int i915_gem_gtt_init(struct drm_device *dev);
static inline void i915_gem_chipset_flush(struct drm_device *dev)
{
- if (to_i915(dev)->info->gen < 6)
+ if (to_i915(dev)->info.gen < 6)
intel_gtt_chipset_flush();
}
int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
@@ -2310,7 +2310,7 @@ static inline bool intel_enable_ppgtt(struct drm_device *dev, bool full)
#ifdef CONFIG_INTEL_IOMMU
/* Disable ppgtt on SNB if VT-d is on. */
- if (to_i915(dev)->info->gen == 6 && intel_iommu_gfx_mapped) {
+ if (to_i915(dev)->info.gen == 6 && intel_iommu_gfx_mapped) {
DRM_INFO("Disabling PPGTT because VT-d is on\n");
return false;
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1ac740e..f098e3a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -180,7 +180,7 @@ i915_gem_init_ioctl(struct drm_device *dev, void *data,
return -EINVAL;
/* GEM with user mode setting was never supported on ilk and later. */
- if (dev_priv->info->gen >= 5)
+ if (dev_priv->info.gen >= 5)
return -ENODEV;
mutex_lock(&dev->struct_mutex);
@@ -1029,7 +1029,7 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;
- if (dev_priv->info->gen >= 6 && can_wait_boost(file_priv)) {
+ if (dev_priv->info.gen >= 6 && can_wait_boost(file_priv)) {
gen6_rps_boost(dev_priv);
if (file_priv)
mod_delayed_work(dev_priv->wq,
@@ -1511,12 +1511,12 @@ i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t gtt_size;
- if (dev_priv->info->gen >= 4 ||
+ if (dev_priv->info.gen >= 4 ||
tiling_mode == I915_TILING_NONE)
return size;
/* Previous chips need a power-of-two fence region when tiling */
- if (dev_priv->info->gen == 3)
+ if (dev_priv->info.gen == 3)
gtt_size = 1024*1024;
else
gtt_size = 512*1024;
@@ -1544,7 +1544,7 @@ i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
* Minimum alignment is 4k (GTT page size), but might be greater
* if a fence register is needed for the object.
*/
- if (dev_priv->info->gen >= 4 || (!fenced && IS_G33(dev)) ||
+ if (dev_priv->info.gen >= 4 || (!fenced && IS_G33(dev)) ||
tiling_mode == I915_TILING_NONE)
return 4096;
@@ -2869,7 +2869,7 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
int fence_reg;
int fence_pitch_shift;
- if (dev_priv->info->gen >= 6) {
+ if (dev_priv->info.gen >= 6) {
fence_reg = FENCE_REG_SANDYBRIDGE_0;
fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
} else {
@@ -3010,7 +3010,7 @@ static void i915_gem_write_fence(struct drm_device *dev, int reg,
"bogus fence setup with stride: 0x%x, tiling mode: %i\n",
obj->stride, obj->tiling_mode);
- switch (dev_priv->info->gen) {
+ switch (dev_priv->info.gen) {
case 8:
case 7:
case 6:
@@ -3556,7 +3556,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
* registers with snooped memory, so relinquish any fences
* currently pointing to our region in the aperture.
*/
- if (dev_priv->info->gen < 6) {
+ if (dev_priv->info.gen < 6) {
ret = i915_gem_object_put_fence(obj);
if (ret)
return ret;
@@ -3960,7 +3960,7 @@ i915_gem_pin_ioctl(struct drm_device *dev, void *data,
struct drm_i915_gem_object *obj;
int ret;
- if (dev_priv->info->gen >= 6)
+ if (dev_priv->info.gen >= 6)
return -ENODEV;
ret = i915_mutex_lock_interruptible(dev);
@@ -4369,7 +4369,7 @@ void i915_gem_init_swizzling(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = dev->dev_private;
- if (dev_priv->info->gen < 5 ||
+ if (dev_priv->info.gen < 5 ||
dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
return;
@@ -4458,7 +4458,7 @@ i915_gem_init_hw(struct drm_device *dev)
drm_i915_private_t *dev_priv = dev->dev_private;
int ret, i;
- if (dev_priv->info->gen < 6 && !intel_enable_gtt())
+ if (dev_priv->info.gen < 6 && !intel_enable_gtt())
return -EIO;
if (dev_priv->ellc_size)
@@ -4676,9 +4676,9 @@ i915_gem_load(struct drm_device *dev)
if (!drm_core_check_feature(dev, DRIVER_MODESET))
dev_priv->fence_reg_start = 3;
- if (dev_priv->info->gen >= 7 && !IS_VALLEYVIEW(dev))
+ if (dev_priv->info.gen >= 7 && !IS_VALLEYVIEW(dev))
dev_priv->num_fence_regs = 32;
- else if (dev_priv->info->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
+ else if (dev_priv->info.gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
dev_priv->num_fence_regs = 16;
else
dev_priv->num_fence_regs = 8;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index d4eb705..662b293 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -113,7 +113,7 @@ static int get_context_size(struct drm_device *dev)
int ret;
u32 reg;
- switch (dev_priv->info->gen) {
+ switch (dev_priv->info.gen) {
case 6:
reg = I915_READ(CXT_SIZE);
ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
@@ -195,7 +195,7 @@ __create_hw_context(struct drm_device *dev,
return ERR_PTR(-ENOMEM);
}
- if (dev_priv->info->gen >= 7) {
+ if (dev_priv->info.gen >= 7) {
ret = i915_gem_object_set_cache_level(ctx->obj,
I915_CACHE_L3_LLC);
/* Failure shouldn't ever happen this early */
@@ -319,7 +319,7 @@ void i915_gem_context_reset(struct drm_device *dev)
* the next switch */
for (i = 0; i < I915_NUM_RINGS; i++) {
struct i915_hw_context *dctx;
- if (!(dev_priv->info->ring_mask & (1<<i)))
+ if (!(dev_priv->info.ring_mask & (1<<i)))
continue;
/* Do a fake switch to the default context */
@@ -380,7 +380,7 @@ int i915_gem_context_init(struct drm_device *dev)
}
for (i = RCS + 1; i < I915_NUM_RINGS; i++) {
- if (!(dev_priv->info->ring_mask & (1<<i)))
+ if (!(dev_priv->info.ring_mask & (1<<i)))
continue;
ring = &dev_priv->ring[i];
@@ -424,7 +424,7 @@ void i915_gem_context_fini(struct drm_device *dev)
for (i = 0; i < I915_NUM_RINGS; i++) {
struct intel_ring_buffer *ring = &dev_priv->ring[i];
- if (!(dev_priv->info->ring_mask & (1<<i)))
+ if (!(dev_priv->info.ring_mask & (1<<i)))
continue;
if (ring->last_context)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 431a65a..f81c1f1 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -278,7 +278,7 @@ relocate_entry_cpu(struct drm_i915_gem_object *obj,
reloc->offset >> PAGE_SHIFT));
*(uint32_t *)(vaddr + page_offset) = reloc->delta;
- if (dev_priv->info->gen >= 8) {
+ if (dev_priv->info.gen >= 8) {
page_offset = offset_in_page(page_offset + sizeof(uint32_t));
if (page_offset == 0) {
@@ -321,7 +321,7 @@ relocate_entry_gtt(struct drm_i915_gem_object *obj,
(reloc_page + offset_in_page(reloc->offset));
iowrite32(reloc->delta, reloc_entry);
- if (dev_priv->info->gen >= 8) {
+ if (dev_priv->info.gen >= 8) {
reloc_entry += 1;
if (offset_in_page(reloc->offset + sizeof(uint32_t)) == 0) {
@@ -408,7 +408,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
/* Check that the relocation address is valid... */
if (unlikely(reloc->offset >
- obj->base.size - (dev_priv->info->gen >= 8 ? 8 : 4))) {
+ obj->base.size - (dev_priv->info.gen >= 8 ? 8 : 4))) {
DRM_DEBUG("Relocation beyond object bounds: "
"obj %p target %d offset %d size %d.\n",
obj, reloc->target_handle,
@@ -545,7 +545,7 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
{
struct drm_i915_gem_object *obj = vma->obj;
struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
- bool has_fenced_gpu_access = to_i915(ring->dev)->info->gen < 4;
+ bool has_fenced_gpu_access = to_i915(ring->dev)->info.gen < 4;
bool need_fence, need_mappable;
u32 flags = (entry->flags & EXEC_OBJECT_NEEDS_GTT) &&
!vma->obj->has_global_gtt_mapping ? GLOBAL_BIND : 0;
@@ -601,7 +601,7 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
struct i915_vma *vma;
struct i915_address_space *vm;
struct list_head ordered_vmas;
- bool has_fenced_gpu_access = to_i915(ring->dev)->info->gen < 4;
+ bool has_fenced_gpu_access = to_i915(ring->dev)->info.gen < 4;
int retry;
if (list_empty(vmas))
@@ -1060,15 +1060,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
case I915_EXEC_CONSTANTS_REL_SURFACE:
if (ring == &dev_priv->ring[RCS] &&
mode != dev_priv->relative_constants_mode) {
- if (dev_priv->info->gen < 4)
+ if (dev_priv->info.gen < 4)
return -EINVAL;
- if (dev_priv->info->gen > 5 &&
+ if (dev_priv->info.gen > 5 &&
mode == I915_EXEC_CONSTANTS_REL_SURFACE)
return -EINVAL;
/* The HW changed the meaning on this bit on gen6 */
- if (dev_priv->info->gen >= 6)
+ if (dev_priv->info.gen >= 6)
mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
}
break;
@@ -1088,7 +1088,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
return -EINVAL;
}
- if (dev_priv->info->gen >= 5) {
+ if (dev_priv->info.gen >= 5) {
DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
return -EINVAL;
}
@@ -1319,7 +1319,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
exec2_list[i].alignment = exec_list[i].alignment;
exec2_list[i].offset = exec_list[i].offset;
- if (dev_priv->info->gen < 4)
+ if (dev_priv->info.gen < 4)
exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
else
exec2_list[i].flags = 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2f76c77..1328943 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -964,7 +964,7 @@ int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
ppgtt->base.dev = dev;
- if (dev_priv->info->gen < 8)
+ if (dev_priv->info.gen < 8)
ret = gen6_ppgtt_init(ppgtt);
else if (IS_GEN8(dev))
ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
@@ -977,7 +977,7 @@ int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
ppgtt->base.total);
i915_init_vm(dev_priv, &ppgtt->base);
- if (dev_priv->info->gen < 8) {
+ if (dev_priv->info.gen < 8) {
gen6_write_pdes(ppgtt);
DRM_DEBUG("Adding PPGTT at offset %x\n",
ppgtt->pd_offset << 10);
@@ -1053,7 +1053,7 @@ void i915_check_and_clear_faults(struct drm_device *dev)
struct intel_ring_buffer *ring;
int i;
- if (dev_priv->info->gen < 6)
+ if (dev_priv->info.gen < 6)
return;
for_each_ring(ring, dev_priv, i) {
@@ -1083,7 +1083,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
/* Don't bother messing with faults pre GEN6 as we have little
* documentation supporting that it's a good idea.
*/
- if (dev_priv->info->gen < 6)
+ if (dev_priv->info.gen < 6)
return;
i915_check_and_clear_faults(dev);
@@ -1124,7 +1124,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
}
- if (dev_priv->info->gen >= 8)
+ if (dev_priv->info.gen >= 8)
return;
list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
@@ -1741,10 +1741,10 @@ int i915_gem_gtt_init(struct drm_device *dev)
struct i915_gtt *gtt = &dev_priv->gtt;
int ret;
- if (dev_priv->info->gen <= 5) {
+ if (dev_priv->info.gen <= 5) {
gtt->gtt_probe = i915_gmch_probe;
gtt->base.cleanup = i915_gmch_remove;
- } else if (dev_priv->info->gen < 8) {
+ } else if (dev_priv->info.gen < 8) {
gtt->gtt_probe = gen6_gmch_probe;
gtt->base.cleanup = gen6_gmch_remove;
if (IS_HASWELL(dev) && dev_priv->ellc_size)
@@ -1753,7 +1753,7 @@ int i915_gem_gtt_init(struct drm_device *dev)
gtt->base.pte_encode = hsw_pte_encode;
else if (IS_VALLEYVIEW(dev))
gtt->base.pte_encode = byt_pte_encode;
- else if (dev_priv->info->gen >= 7)
+ else if (dev_priv->info.gen >= 7)
gtt->base.pte_encode = ivb_pte_encode;
else
gtt->base.pte_encode = snb_pte_encode;
@@ -1791,7 +1791,7 @@ static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
vma->vm = vm;
vma->obj = obj;
- switch (to_i915(vm->dev)->info->gen) {
+ switch (to_i915(vm->dev)->info.gen) {
case 8:
case 7:
case 6:
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index e804c49..84617a5 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -60,7 +60,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
* XXX However gen2 requires an unavailable symbol.
*/
base = 0;
- if (dev_priv->info->gen >= 3) {
+ if (dev_priv->info.gen >= 3) {
/* Read Graphics Base of Stolen Memory directly */
pci_read_config_dword(dev->pdev, 0x5c, &base);
base &= ~((1<<20) - 1);
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 2d3535f..afb67a8 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -94,7 +94,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
if (IS_VALLEYVIEW(dev)) {
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
- } else if (dev_priv->info->gen >= 6) {
+ } else if (dev_priv->info.gen >= 6) {
uint32_t dimm_c0, dimm_c1;
dimm_c0 = I915_READ(MAD_DIMM_C0);
dimm_c1 = I915_READ(MAD_DIMM_C1);
@@ -220,10 +220,10 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
/* check maximum stride & object size */
/* i965+ stores the end address of the gtt mapping in the fence
* reg, so dont bother to check the size */
- if (dev_priv->info->gen >= 7) {
+ if (dev_priv->info.gen >= 7) {
if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
return false;
- } else if (dev_priv->info->gen >= 4) {
+ } else if (dev_priv->info.gen >= 4) {
if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
return false;
} else {
@@ -243,7 +243,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
return false;
/* 965+ just needs multiples of tile width */
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
if (stride & (tile_width - 1))
return false;
return true;
@@ -266,10 +266,10 @@ i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
if (tiling_mode == I915_TILING_NONE)
return true;
- if (dev_priv->info->gen >= 4)
+ if (dev_priv->info.gen >= 4)
return true;
- if (dev_priv->info->gen == 3) {
+ if (dev_priv->info.gen == 3) {
if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
return false;
} else {
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index c3f35a4..8b2b96e 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -249,14 +249,14 @@ static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr[ring]);
err_printf(m, " BB_STATE: 0x%08x\n", error->bbstate[ring]);
err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
}
err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
- if (dev_priv->info->gen >= 6) {
+ if (dev_priv->info.gen >= 6) {
err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
@@ -322,12 +322,12 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
error->extra_instdone[i]);
- if (dev_priv->info->gen >= 6) {
+ if (dev_priv->info.gen >= 6) {
err_printf(m, "ERROR: 0x%08x\n", error->error);
err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
}
- if (dev_priv->info->gen == 7)
+ if (dev_priv->info.gen == 7)
err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
for_each_ring(ring, dev_priv, i)
@@ -630,7 +630,7 @@ static void i915_gem_record_fences(struct drm_device *dev,
int i;
/* Fences */
- switch (dev_priv->info->gen) {
+ switch (dev_priv->info.gen) {
case 8:
case 7:
case 6:
@@ -665,13 +665,13 @@ static bool is_active_vm(struct i915_address_space *vm,
struct drm_i915_private *dev_priv = dev->dev_private;
struct i915_hw_ppgtt *ppgtt;
- if (dev_priv->info->gen < 7)
+ if (dev_priv->info.gen < 7)
return i915_is_ggtt(vm);
/* FIXME: This ignores that the global gtt vm is also on this list. */
ppgtt = container_of(vm, struct i915_hw_ppgtt, base);
- if (dev_priv->info->gen >= 8) {
+ if (dev_priv->info.gen >= 8) {
u64 pdp0 = (u64)I915_READ(GEN8_RING_PDP_UDW(ring, 0)) << 32;
pdp0 |= I915_READ(GEN8_RING_PDP_LDW(ring, 0));
return pdp0 == ppgtt->pd_dma_addr[0];
@@ -742,7 +742,7 @@ static void i915_record_ring_state(struct drm_device *dev,
{
struct drm_i915_private *dev_priv = dev->dev_private;
- if (dev_priv->info->gen >= 6) {
+ if (dev_priv->info.gen >= 6) {
error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
error->semaphore_mboxes[ring->id][0]
@@ -759,14 +759,14 @@ static void i915_record_ring_state(struct drm_device *dev,
error->semaphore_seqno[ring->id][2] = ring->sync_seqno[2];
}
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
error->bbaddr[ring->id] = I915_READ(RING_BBADDR(ring->mmio_base));
- if (dev_priv->info->gen >= 8)
+ if (dev_priv->info.gen >= 8)
error->bbaddr[ring->id] |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
error->bbstate[ring->id] = I915_READ(RING_BBSTATE(ring->mmio_base));
} else {
@@ -973,26 +973,26 @@ void i915_capture_error_state(struct drm_device *dev)
else
error->ier = I915_READ(IER);
- if (dev_priv->info->gen >= 6)
+ if (dev_priv->info.gen >= 6)
error->derrmr = I915_READ(DERRMR);
if (IS_VALLEYVIEW(dev))
error->forcewake = I915_READ(FORCEWAKE_VLV);
- else if (dev_priv->info->gen >= 7)
+ else if (dev_priv->info.gen >= 7)
error->forcewake = I915_READ(FORCEWAKE_MT);
- else if (dev_priv->info->gen == 6)
+ else if (dev_priv->info.gen == 6)
error->forcewake = I915_READ(FORCEWAKE);
if (!HAS_PCH_SPLIT(dev))
for_each_pipe(pipe)
error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
- if (dev_priv->info->gen >= 6) {
+ if (dev_priv->info.gen >= 6) {
error->error = I915_READ(ERROR_GEN6);
error->done_reg = I915_READ(DONE_REG);
}
- if (dev_priv->info->gen == 7)
+ if (dev_priv->info.gen == 7)
error->err_int = I915_READ(GEN7_ERR_INT);
i915_get_extra_instdone(dev, error->extra_instdone);
@@ -1069,7 +1069,7 @@ void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
struct drm_i915_private *dev_priv = dev->dev_private;
memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
- switch (dev_priv->info->gen) {
+ switch (dev_priv->info.gen) {
case 2:
case 3:
instdone[0] = I915_READ(INSTDONE);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5170e4d..f5991ed 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -505,7 +505,7 @@ static void i915_enable_asle_pipestat(struct drm_device *dev)
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE);
- if (dev_priv->info->gen >= 4)
+ if (dev_priv->info.gen >= 4)
i915_enable_pipestat(dev_priv, PIPE_A,
PIPE_LEGACY_BLC_EVENT_ENABLE);
@@ -639,13 +639,13 @@ static bool intel_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
reg = ISR;
- } else if (dev_priv->info->gen < 5) {
+ } else if (dev_priv->info.gen < 5) {
status = pipe == PIPE_A ?
I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
reg = ISR;
- } else if (dev_priv->info->gen < 7) {
+ } else if (dev_priv->info.gen < 7) {
status = pipe == PIPE_A ?
DE_PIPEA_VBLANK :
DE_PIPEB_VBLANK;
@@ -713,7 +713,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
if (stime)
*stime = ktime_get();
- if (IS_GEN2(dev) || IS_G4X(dev) || dev_priv->info->gen >= 5) {
+ if (IS_GEN2(dev) || IS_G4X(dev) || dev_priv->info.gen >= 5) {
/* No obvious pixelcount register. Only query vertical
* scanout position from Display scan line register.
*/
@@ -767,7 +767,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
else
position += vtotal - vbl_end;
- if (IS_GEN2(dev) || IS_G4X(dev) || dev_priv->info->gen >= 5) {
+ if (IS_GEN2(dev) || IS_G4X(dev) || dev_priv->info.gen >= 5) {
*vpos = position;
*hpos = 0;
} else {
@@ -790,7 +790,7 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_crtc *crtc;
- if (pipe < 0 || pipe >= dev_priv->info->num_pipes) {
+ if (pipe < 0 || pipe >= dev_priv->info.num_pipes) {
DRM_ERROR("Invalid crtc %d\n", pipe);
return -EINVAL;
}
@@ -1367,12 +1367,12 @@ static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t res1, res2;
- if (dev_priv->info->gen >= 3)
+ if (dev_priv->info.gen >= 3)
res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
else
res1 = 0;
- if (dev_priv->info->gen >= 5 || IS_G4X(dev))
+ if (dev_priv->info.gen >= 5 || IS_G4X(dev))
res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
else
res2 = 0;
@@ -1756,7 +1756,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
gt_iir = I915_READ(GTIIR);
if (gt_iir) {
- if (dev_priv->info->gen >= 6)
+ if (dev_priv->info.gen >= 6)
snb_gt_irq_handler(dev, dev_priv, gt_iir);
else
ilk_gt_irq_handler(dev, dev_priv, gt_iir);
@@ -1766,7 +1766,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
de_iir = I915_READ(DEIIR);
if (de_iir) {
- if (dev_priv->info->gen >= 7)
+ if (dev_priv->info.gen >= 7)
ivb_display_irq_handler(dev, de_iir);
else
ilk_display_irq_handler(dev, de_iir);
@@ -1774,7 +1774,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
ret = IRQ_HANDLED;
}
- if (dev_priv->info->gen >= 6) {
+ if (dev_priv->info.gen >= 6) {
u32 pm_iir = I915_READ(GEN6_PMIIR);
if (pm_iir) {
gen6_rps_irq_handler(dev_priv, pm_iir);
@@ -2064,7 +2064,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
for (i = 0; i < ARRAY_SIZE(instdone); i++)
pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
- if (dev_priv->info->gen < 4) {
+ if (dev_priv->info.gen < 4) {
u32 ipeir = I915_READ(IPEIR);
pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
@@ -2171,7 +2171,7 @@ static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, in
/* Potential stall - if we see that the flip has happened, assume a missed interrupt */
obj = work->pending_flip_obj;
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
int dspsurf = DSPSURF(intel_crtc->plane);
stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
i915_gem_obj_ggtt_offset(obj);
@@ -2202,7 +2202,7 @@ static int i915_enable_vblank(struct drm_device *dev, int pipe)
return -EINVAL;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- if (dev_priv->info->gen >= 4)
+ if (dev_priv->info.gen >= 4)
i915_enable_pipestat(dev_priv, pipe,
PIPE_START_VBLANK_INTERRUPT_ENABLE);
else
@@ -2210,7 +2210,7 @@ static int i915_enable_vblank(struct drm_device *dev, int pipe)
PIPE_VBLANK_INTERRUPT_ENABLE);
/* maintain vblank delivery even in deep C-states */
- if (dev_priv->info->gen == 3)
+ if (dev_priv->info.gen == 3)
I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@@ -2221,7 +2221,7 @@ static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
unsigned long irqflags;
- uint32_t bit = (dev_priv->info->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
+ uint32_t bit = (dev_priv->info.gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
DE_PIPE_VBLANK(pipe);
if (!i915_pipe_enabled(dev, pipe))
@@ -2282,7 +2282,7 @@ static void i915_disable_vblank(struct drm_device *dev, int pipe)
unsigned long irqflags;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- if (dev_priv->info->gen == 3)
+ if (dev_priv->info.gen == 3)
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
i915_disable_pipestat(dev_priv, pipe,
@@ -2295,7 +2295,7 @@ static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
unsigned long irqflags;
- uint32_t bit = (dev_priv->info->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
+ uint32_t bit = (dev_priv->info.gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
DE_PIPE_VBLANK(pipe);
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -2436,7 +2436,7 @@ ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
return HANGCHECK_KICK;
}
- if (dev_priv->info->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
+ if (dev_priv->info.gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
switch (semaphore_passed(ring)) {
default:
return HANGCHECK_HUNG;
@@ -2612,7 +2612,7 @@ static void gen5_gt_irq_preinstall(struct drm_device *dev)
I915_WRITE(GTIER, 0x0);
POSTING_READ(GTIER);
- if (dev_priv->info->gen >= 6) {
+ if (dev_priv->info.gen >= 6) {
/* and PM */
I915_WRITE(GEN6_PMIMR, 0xffffffff);
I915_WRITE(GEN6_PMIER, 0x0);
@@ -2800,7 +2800,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
I915_WRITE(GTIER, gt_irqs);
POSTING_READ(GTIER);
- if (dev_priv->info->gen >= 6) {
+ if (dev_priv->info.gen >= 6) {
pm_irqs |= GEN6_PM_RPS_EVENTS;
if (HAS_VEBOX(dev))
@@ -2820,7 +2820,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
u32 display_mask, extra_mask;
- if (dev_priv->info->gen >= 7) {
+ if (dev_priv->info.gen >= 7) {
display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
DE_PLANEB_FLIP_DONE_IVB |
@@ -3799,7 +3799,7 @@ void intel_irq_init(struct drm_device *dev)
if (IS_GEN2(dev)) {
dev->max_vblank_count = 0;
dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
- } else if (IS_G4X(dev) || dev_priv->info->gen >= 5) {
+ } else if (IS_G4X(dev) || dev_priv->info.gen >= 5) {
dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
dev->driver->get_vblank_counter = gm45_get_vblank_counter;
} else {
@@ -3837,12 +3837,12 @@ void intel_irq_init(struct drm_device *dev)
dev->driver->disable_vblank = ironlake_disable_vblank;
dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
} else {
- if (dev_priv->info->gen == 2) {
+ if (dev_priv->info.gen == 2) {
dev->driver->irq_preinstall = i8xx_irq_preinstall;
dev->driver->irq_postinstall = i8xx_irq_postinstall;
dev->driver->irq_handler = i8xx_irq_handler;
dev->driver->irq_uninstall = i8xx_irq_uninstall;
- } else if (dev_priv->info->gen == 3) {
+ } else if (dev_priv->info.gen == 3) {
dev->driver->irq_preinstall = i915_irq_preinstall;
dev->driver->irq_postinstall = i915_irq_postinstall;
dev->driver->irq_uninstall = i915_irq_uninstall;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a699efd..6e3dd6c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1214,8 +1214,8 @@
#define VGA1_PD_P1_DIV_2 (1 << 13)
#define VGA1_PD_P1_SHIFT 8
#define VGA1_PD_P1_MASK (0x1f << 8)
-#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014)
-#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018)
+#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
+#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
#define DPLL_VCO_ENABLE (1 << 31)
#define DPLL_SDVO_HIGH_SPEED (1 << 30)
@@ -1278,7 +1278,7 @@
#define SDVO_MULTIPLIER_MASK 0x000000ff
#define SDVO_MULTIPLIER_SHIFT_HIRES 4
#define SDVO_MULTIPLIER_SHIFT_VGA 0
-#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */
+#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) /* 965+ only */
/*
* UDI pixel divider, controlling how many pixels are stuffed into a packet.
*
@@ -1315,7 +1315,7 @@
*/
#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
-#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */
+#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) /* 965+ only */
#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
#define _FPA0 0x06040
@@ -1348,7 +1348,7 @@
#define DSTATE_PLL_D3_OFF (1<<3)
#define DSTATE_GFX_CLOCK_GATING (1<<1)
#define DSTATE_DOT_CLOCK_GATING (1<<0)
-#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200)
+#define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)
# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
@@ -1473,8 +1473,8 @@
* Palette regs
*/
-#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000)
-#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800)
+#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
+#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
/* MCH MMIO space */
@@ -1862,7 +1862,7 @@
*/
/* Pipe A CRC regs */
-#define _PIPE_CRC_CTL_A (dev_priv->info->display_mmio_offset + 0x60050)
+#define _PIPE_CRC_CTL_A (dev_priv->info.display_mmio_offset + 0x60050)
#define PIPE_CRC_ENABLE (1 << 31)
/* ivb+ source selection */
#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
@@ -1902,11 +1902,11 @@
#define _PIPE_CRC_RES_4_A_IVB 0x60070
#define _PIPE_CRC_RES_5_A_IVB 0x60074
-#define _PIPE_CRC_RES_RED_A (dev_priv->info->display_mmio_offset + 0x60060)
-#define _PIPE_CRC_RES_GREEN_A (dev_priv->info->display_mmio_offset + 0x60064)
-#define _PIPE_CRC_RES_BLUE_A (dev_priv->info->display_mmio_offset + 0x60068)
-#define _PIPE_CRC_RES_RES1_A_I915 (dev_priv->info->display_mmio_offset + 0x6006c)
-#define _PIPE_CRC_RES_RES2_A_G4X (dev_priv->info->display_mmio_offset + 0x60080)
+#define _PIPE_CRC_RES_RED_A (dev_priv->info.display_mmio_offset + 0x60060)
+#define _PIPE_CRC_RES_GREEN_A (dev_priv->info.display_mmio_offset + 0x60064)
+#define _PIPE_CRC_RES_BLUE_A (dev_priv->info.display_mmio_offset + 0x60068)
+#define _PIPE_CRC_RES_RES1_A_I915 (dev_priv->info.display_mmio_offset + 0x6006c)
+#define _PIPE_CRC_RES_RES2_A_G4X (dev_priv->info.display_mmio_offset + 0x60080)
/* Pipe B CRC regs */
#define _PIPE_CRC_RES_1_B_IVB 0x61064
@@ -1939,26 +1939,26 @@
_PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_G4X, 0x01000)
/* Pipe A timing regs */
-#define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000)
-#define _HBLANK_A (dev_priv->info->display_mmio_offset + 0x60004)
-#define _HSYNC_A (dev_priv->info->display_mmio_offset + 0x60008)
-#define _VTOTAL_A (dev_priv->info->display_mmio_offset + 0x6000c)
-#define _VBLANK_A (dev_priv->info->display_mmio_offset + 0x60010)
-#define _VSYNC_A (dev_priv->info->display_mmio_offset + 0x60014)
-#define _PIPEASRC (dev_priv->info->display_mmio_offset + 0x6001c)
-#define _BCLRPAT_A (dev_priv->info->display_mmio_offset + 0x60020)
-#define _VSYNCSHIFT_A (dev_priv->info->display_mmio_offset + 0x60028)
+#define _HTOTAL_A (dev_priv->info.display_mmio_offset + 0x60000)
+#define _HBLANK_A (dev_priv->info.display_mmio_offset + 0x60004)
+#define _HSYNC_A (dev_priv->info.display_mmio_offset + 0x60008)
+#define _VTOTAL_A (dev_priv->info.display_mmio_offset + 0x6000c)
+#define _VBLANK_A (dev_priv->info.display_mmio_offset + 0x60010)
+#define _VSYNC_A (dev_priv->info.display_mmio_offset + 0x60014)
+#define _PIPEASRC (dev_priv->info.display_mmio_offset + 0x6001c)
+#define _BCLRPAT_A (dev_priv->info.display_mmio_offset + 0x60020)
+#define _VSYNCSHIFT_A (dev_priv->info.display_mmio_offset + 0x60028)
/* Pipe B timing regs */
-#define _HTOTAL_B (dev_priv->info->display_mmio_offset + 0x61000)
-#define _HBLANK_B (dev_priv->info->display_mmio_offset + 0x61004)
-#define _HSYNC_B (dev_priv->info->display_mmio_offset + 0x61008)
-#define _VTOTAL_B (dev_priv->info->display_mmio_offset + 0x6100c)
-#define _VBLANK_B (dev_priv->info->display_mmio_offset + 0x61010)
-#define _VSYNC_B (dev_priv->info->display_mmio_offset + 0x61014)
-#define _PIPEBSRC (dev_priv->info->display_mmio_offset + 0x6101c)
-#define _BCLRPAT_B (dev_priv->info->display_mmio_offset + 0x61020)
-#define _VSYNCSHIFT_B (dev_priv->info->display_mmio_offset + 0x61028)
+#define _HTOTAL_B (dev_priv->info.display_mmio_offset + 0x61000)
+#define _HBLANK_B (dev_priv->info.display_mmio_offset + 0x61004)
+#define _HSYNC_B (dev_priv->info.display_mmio_offset + 0x61008)
+#define _VTOTAL_B (dev_priv->info.display_mmio_offset + 0x6100c)
+#define _VBLANK_B (dev_priv->info.display_mmio_offset + 0x61010)
+#define _VSYNC_B (dev_priv->info.display_mmio_offset + 0x61014)
+#define _PIPEBSRC (dev_priv->info.display_mmio_offset + 0x6101c)
+#define _BCLRPAT_B (dev_priv->info.display_mmio_offset + 0x61020)
+#define _VSYNCSHIFT_B (dev_priv->info.display_mmio_offset + 0x61028)
#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
@@ -2084,7 +2084,7 @@
/* Hotplug control (945+ only) */
-#define PORT_HOTPLUG_EN (dev_priv->info->display_mmio_offset + 0x61110)
+#define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)
#define PORTB_HOTPLUG_INT_EN (1 << 29)
#define PORTC_HOTPLUG_INT_EN (1 << 28)
#define PORTD_HOTPLUG_INT_EN (1 << 27)
@@ -2114,7 +2114,7 @@
#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
-#define PORT_HOTPLUG_STAT (dev_priv->info->display_mmio_offset + 0x61114)
+#define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)
/*
* HDMI/DP bits are gen4+
*
@@ -2386,7 +2386,7 @@
#define PP_DIVISOR 0x61210
/* Panel fitting */
-#define PFIT_CONTROL (dev_priv->info->display_mmio_offset + 0x61230)
+#define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)
#define PFIT_ENABLE (1 << 31)
#define PFIT_PIPE_MASK (3 << 29)
#define PFIT_PIPE_SHIFT 29
@@ -2404,7 +2404,7 @@
#define PFIT_SCALING_PROGRAMMED (1 << 26)
#define PFIT_SCALING_PILLAR (2 << 26)
#define PFIT_SCALING_LETTER (3 << 26)
-#define PFIT_PGM_RATIOS (dev_priv->info->display_mmio_offset + 0x61234)
+#define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
/* Pre-965 */
#define PFIT_VERT_SCALE_SHIFT 20
#define PFIT_VERT_SCALE_MASK 0xfff00000
@@ -2416,25 +2416,25 @@
#define PFIT_HORIZ_SCALE_SHIFT_965 0
#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
-#define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
+#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
-#define _VLV_BLC_PWM_CTL2_A (dev_priv->info->display_mmio_offset + 0x61250)
-#define _VLV_BLC_PWM_CTL2_B (dev_priv->info->display_mmio_offset + 0x61350)
+#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
+#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
_VLV_BLC_PWM_CTL2_B)
-#define _VLV_BLC_PWM_CTL_A (dev_priv->info->display_mmio_offset + 0x61254)
-#define _VLV_BLC_PWM_CTL_B (dev_priv->info->display_mmio_offset + 0x61354)
+#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
+#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
_VLV_BLC_PWM_CTL_B)
-#define _VLV_BLC_HIST_CTL_A (dev_priv->info->display_mmio_offset + 0x61260)
-#define _VLV_BLC_HIST_CTL_B (dev_priv->info->display_mmio_offset + 0x61360)
+#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
+#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
_VLV_BLC_HIST_CTL_B)
/* Backlight control */
-#define BLC_PWM_CTL2 (dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */
+#define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
#define BLM_PWM_ENABLE (1 << 31)
#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
#define BLM_PIPE_SELECT (1 << 29)
@@ -2457,7 +2457,7 @@
#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
#define BLM_PHASE_IN_INCR_SHIFT (0)
#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
-#define BLC_PWM_CTL (dev_priv->info->display_mmio_offset + 0x61254)
+#define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)
/*
* This is the most significant 15 bits of the number of backlight cycles in a
* complete cycle of the modulated backlight control.
@@ -2479,7 +2479,7 @@
#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
-#define BLC_HIST_CTL (dev_priv->info->display_mmio_offset + 0x61260)
+#define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
/* New registers for PCH-split platforms. Safe where new bits show up, the
* register layout machtes with gen4 BLC_PWM_CTL[12]. */
@@ -3173,10 +3173,10 @@
/* Display & cursor control */
/* Pipe A */
-#define _PIPEADSL (dev_priv->info->display_mmio_offset + 0x70000)
+#define _PIPEADSL (dev_priv->info.display_mmio_offset + 0x70000)
#define DSL_LINEMASK_GEN2 0x00000fff
#define DSL_LINEMASK_GEN3 0x00001fff
-#define _PIPEACONF (dev_priv->info->display_mmio_offset + 0x70008)
+#define _PIPEACONF (dev_priv->info.display_mmio_offset + 0x70008)
#define PIPECONF_ENABLE (1<<31)
#define PIPECONF_DISABLE 0
#define PIPECONF_DOUBLE_WIDE (1<<30)
@@ -3219,7 +3219,7 @@
#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
-#define _PIPEASTAT (dev_priv->info->display_mmio_offset + 0x70024)
+#define _PIPEASTAT (dev_priv->info.display_mmio_offset + 0x70024)
#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
#define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30)
#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
@@ -3318,7 +3318,7 @@
#define DSPARB_BEND_SHIFT 9 /* on 855 */
#define DSPARB_AEND_SHIFT 0
-#define DSPFW1 (dev_priv->info->display_mmio_offset + 0x70034)
+#define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
#define DSPFW_SR_SHIFT 23
#define DSPFW_SR_MASK (0x1ff<<23)
#define DSPFW_CURSORB_SHIFT 16
@@ -3326,11 +3326,11 @@
#define DSPFW_PLANEB_SHIFT 8
#define DSPFW_PLANEB_MASK (0x7f<<8)
#define DSPFW_PLANEA_MASK (0x7f)
-#define DSPFW2 (dev_priv->info->display_mmio_offset + 0x70038)
+#define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
#define DSPFW_CURSORA_MASK 0x00003f00
#define DSPFW_CURSORA_SHIFT 8
#define DSPFW_PLANEC_MASK (0x7f)
-#define DSPFW3 (dev_priv->info->display_mmio_offset + 0x7003c)
+#define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
#define DSPFW_HPLL_SR_EN (1<<31)
#define DSPFW_CURSOR_SR_SHIFT 24
#define PINEVIEW_SELF_REFRESH_EN (1<<30)
@@ -3338,8 +3338,8 @@
#define DSPFW_HPLL_CURSOR_SHIFT 16
#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
#define DSPFW_HPLL_SR_MASK (0x1ff)
-#define DSPFW4 (dev_priv->info->display_mmio_offset + 0x70070)
-#define DSPFW7 (dev_priv->info->display_mmio_offset + 0x7007c)
+#define DSPFW4 (dev_priv->info.display_mmio_offset + 0x70070)
+#define DSPFW7 (dev_priv->info.display_mmio_offset + 0x7007c)
/* drain latency register values*/
#define DRAIN_LATENCY_PRECISION_32 32
@@ -3463,12 +3463,12 @@
#define PIPE_PIXEL_MASK 0x00ffffff
#define PIPE_PIXEL_SHIFT 0
/* GM45+ just has to be different */
-#define _PIPEA_FRMCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x70040)
-#define _PIPEA_FLIPCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x70044)
+#define _PIPEA_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x70040)
+#define _PIPEA_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x70044)
#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
/* Cursor A & B regs */
-#define _CURACNTR (dev_priv->info->display_mmio_offset + 0x70080)
+#define _CURACNTR (dev_priv->info.display_mmio_offset + 0x70080)
/* Old style CUR*CNTR flags (desktop 8xx) */
#define CURSOR_ENABLE 0x80000000
#define CURSOR_GAMMA_ENABLE 0x40000000
@@ -3491,16 +3491,16 @@
#define MCURSOR_PIPE_B (1 << 28)
#define MCURSOR_GAMMA_ENABLE (1 << 26)
#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
-#define _CURABASE (dev_priv->info->display_mmio_offset + 0x70084)
-#define _CURAPOS (dev_priv->info->display_mmio_offset + 0x70088)
+#define _CURABASE (dev_priv->info.display_mmio_offset + 0x70084)
+#define _CURAPOS (dev_priv->info.display_mmio_offset + 0x70088)
#define CURSOR_POS_MASK 0x007FF
#define CURSOR_POS_SIGN 0x8000
#define CURSOR_X_SHIFT 0
#define CURSOR_Y_SHIFT 16
#define CURSIZE 0x700a0
-#define _CURBCNTR (dev_priv->info->display_mmio_offset + 0x700c0)
-#define _CURBBASE (dev_priv->info->display_mmio_offset + 0x700c4)
-#define _CURBPOS (dev_priv->info->display_mmio_offset + 0x700c8)
+#define _CURBCNTR (dev_priv->info.display_mmio_offset + 0x700c0)
+#define _CURBBASE (dev_priv->info.display_mmio_offset + 0x700c4)
+#define _CURBPOS (dev_priv->info.display_mmio_offset + 0x700c8)
#define _CURBCNTR_IVB 0x71080
#define _CURBBASE_IVB 0x71084
@@ -3515,7 +3515,7 @@
#define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
/* Display A control */
-#define _DSPACNTR (dev_priv->info->display_mmio_offset + 0x70180)
+#define _DSPACNTR (dev_priv->info.display_mmio_offset + 0x70180)
#define DISPLAY_PLANE_ENABLE (1<<31)
#define DISPLAY_PLANE_DISABLE 0
#define DISPPLANE_GAMMA_ENABLE (1<<30)
@@ -3549,14 +3549,14 @@
#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
#define DISPPLANE_TILED (1<<10)
-#define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184)
-#define _DSPASTRIDE (dev_priv->info->display_mmio_offset + 0x70188)
-#define _DSPAPOS (dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */
-#define _DSPASIZE (dev_priv->info->display_mmio_offset + 0x70190)
-#define _DSPASURF (dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */
-#define _DSPATILEOFF (dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */
-#define _DSPAOFFSET (dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */
-#define _DSPASURFLIVE (dev_priv->info->display_mmio_offset + 0x701AC)
+#define _DSPAADDR (dev_priv->info.display_mmio_offset + 0x70184)
+#define _DSPASTRIDE (dev_priv->info.display_mmio_offset + 0x70188)
+#define _DSPAPOS (dev_priv->info.display_mmio_offset + 0x7018C) /* reserved */
+#define _DSPASIZE (dev_priv->info.display_mmio_offset + 0x70190)
+#define _DSPASURF (dev_priv->info.display_mmio_offset + 0x7019C) /* 965+ only */
+#define _DSPATILEOFF (dev_priv->info.display_mmio_offset + 0x701A4) /* 965+ only */
+#define _DSPAOFFSET (dev_priv->info.display_mmio_offset + 0x701A4) /* HSW */
+#define _DSPASURFLIVE (dev_priv->info.display_mmio_offset + 0x701AC)
#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
@@ -3577,44 +3577,44 @@
(I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
/* VBIOS flags */
-#define SWF00 (dev_priv->info->display_mmio_offset + 0x71410)
-#define SWF01 (dev_priv->info->display_mmio_offset + 0x71414)
-#define SWF02 (dev_priv->info->display_mmio_offset + 0x71418)
-#define SWF03 (dev_priv->info->display_mmio_offset + 0x7141c)
-#define SWF04 (dev_priv->info->display_mmio_offset + 0x71420)
-#define SWF05 (dev_priv->info->display_mmio_offset + 0x71424)
-#define SWF06 (dev_priv->info->display_mmio_offset + 0x71428)
-#define SWF10 (dev_priv->info->display_mmio_offset + 0x70410)
-#define SWF11 (dev_priv->info->display_mmio_offset + 0x70414)
-#define SWF14 (dev_priv->info->display_mmio_offset + 0x71420)
-#define SWF30 (dev_priv->info->display_mmio_offset + 0x72414)
-#define SWF31 (dev_priv->info->display_mmio_offset + 0x72418)
-#define SWF32 (dev_priv->info->display_mmio_offset + 0x7241c)
+#define SWF00 (dev_priv->info.display_mmio_offset + 0x71410)
+#define SWF01 (dev_priv->info.display_mmio_offset + 0x71414)
+#define SWF02 (dev_priv->info.display_mmio_offset + 0x71418)
+#define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c)
+#define SWF04 (dev_priv->info.display_mmio_offset + 0x71420)
+#define SWF05 (dev_priv->info.display_mmio_offset + 0x71424)
+#define SWF06 (dev_priv->info.display_mmio_offset + 0x71428)
+#define SWF10 (dev_priv->info.display_mmio_offset + 0x70410)
+#define SWF11 (dev_priv->info.display_mmio_offset + 0x70414)
+#define SWF14 (dev_priv->info.display_mmio_offset + 0x71420)
+#define SWF30 (dev_priv->info.display_mmio_offset + 0x72414)
+#define SWF31 (dev_priv->info.display_mmio_offset + 0x72418)
+#define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c)
/* Pipe B */
-#define _PIPEBDSL (dev_priv->info->display_mmio_offset + 0x71000)
-#define _PIPEBCONF (dev_priv->info->display_mmio_offset + 0x71008)
-#define _PIPEBSTAT (dev_priv->info->display_mmio_offset + 0x71024)
+#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
+#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
+#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
#define _PIPEBFRAMEHIGH 0x71040
#define _PIPEBFRAMEPIXEL 0x71044
-#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x71040)
-#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x71044)
+#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040)
+#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044)
/* Display B control */
-#define _DSPBCNTR (dev_priv->info->display_mmio_offset + 0x71180)
+#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
#define DISPPLANE_ALPHA_TRANS_DISABLE 0
#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
-#define _DSPBADDR (dev_priv->info->display_mmio_offset + 0x71184)
-#define _DSPBSTRIDE (dev_priv->info->display_mmio_offset + 0x71188)
-#define _DSPBPOS (dev_priv->info->display_mmio_offset + 0x7118C)
-#define _DSPBSIZE (dev_priv->info->display_mmio_offset + 0x71190)
-#define _DSPBSURF (dev_priv->info->display_mmio_offset + 0x7119C)
-#define _DSPBTILEOFF (dev_priv->info->display_mmio_offset + 0x711A4)
-#define _DSPBOFFSET (dev_priv->info->display_mmio_offset + 0x711A4)
-#define _DSPBSURFLIVE (dev_priv->info->display_mmio_offset + 0x711AC)
+#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
+#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
+#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
+#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
+#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
+#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
+#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
+#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
/* Sprite A control */
#define _DVSACNTR 0x72180
@@ -3863,39 +3863,39 @@
#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
-#define _PIPEA_DATA_M1 (dev_priv->info->display_mmio_offset + 0x60030)
+#define _PIPEA_DATA_M1 (dev_priv->info.display_mmio_offset + 0x60030)
#define PIPE_DATA_M1_OFFSET 0
-#define _PIPEA_DATA_N1 (dev_priv->info->display_mmio_offset + 0x60034)
+#define _PIPEA_DATA_N1 (dev_priv->info.display_mmio_offset + 0x60034)
#define PIPE_DATA_N1_OFFSET 0
-#define _PIPEA_DATA_M2 (dev_priv->info->display_mmio_offset + 0x60038)
+#define _PIPEA_DATA_M2 (dev_priv->info.display_mmio_offset + 0x60038)
#define PIPE_DATA_M2_OFFSET 0
-#define _PIPEA_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6003c)
+#define _PIPEA_DATA_N2 (dev_priv->info.display_mmio_offset + 0x6003c)
#define PIPE_DATA_N2_OFFSET 0
-#define _PIPEA_LINK_M1 (dev_priv->info->display_mmio_offset + 0x60040)
+#define _PIPEA_LINK_M1 (dev_priv->info.display_mmio_offset + 0x60040)
#define PIPE_LINK_M1_OFFSET 0
-#define _PIPEA_LINK_N1 (dev_priv->info->display_mmio_offset + 0x60044)
+#define _PIPEA_LINK_N1 (dev_priv->info.display_mmio_offset + 0x60044)
#define PIPE_LINK_N1_OFFSET 0
-#define _PIPEA_LINK_M2 (dev_priv->info->display_mmio_offset + 0x60048)
+#define _PIPEA_LINK_M2 (dev_priv->info.display_mmio_offset + 0x60048)
#define PIPE_LINK_M2_OFFSET 0
-#define _PIPEA_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6004c)
+#define _PIPEA_LINK_N2 (dev_priv->info.display_mmio_offset + 0x6004c)
#define PIPE_LINK_N2_OFFSET 0
/* PIPEB timing regs are same start from 0x61000 */
-#define _PIPEB_DATA_M1 (dev_priv->info->display_mmio_offset + 0x61030)
-#define _PIPEB_DATA_N1 (dev_priv->info->display_mmio_offset + 0x61034)
+#define _PIPEB_DATA_M1 (dev_priv->info.display_mmio_offset + 0x61030)
+#define _PIPEB_DATA_N1 (dev_priv->info.display_mmio_offset + 0x61034)
-#define _PIPEB_DATA_M2 (dev_priv->info->display_mmio_offset + 0x61038)
-#define _PIPEB_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6103c)
+#define _PIPEB_DATA_M2 (dev_priv->info.display_mmio_offset + 0x61038)
+#define _PIPEB_DATA_N2 (dev_priv->info.display_mmio_offset + 0x6103c)
-#define _PIPEB_LINK_M1 (dev_priv->info->display_mmio_offset + 0x61040)
-#define _PIPEB_LINK_N1 (dev_priv->info->display_mmio_offset + 0x61044)
+#define _PIPEB_LINK_M1 (dev_priv->info.display_mmio_offset + 0x61040)
+#define _PIPEB_LINK_N1 (dev_priv->info.display_mmio_offset + 0x61044)
-#define _PIPEB_LINK_M2 (dev_priv->info->display_mmio_offset + 0x61048)
-#define _PIPEB_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6104c)
+#define _PIPEB_LINK_M2 (dev_priv->info.display_mmio_offset + 0x61048)
+#define _PIPEB_LINK_N2 (dev_priv->info.display_mmio_offset + 0x6104c)
#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
@@ -5012,7 +5012,7 @@
#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
-#define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020)
+#define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
#define INTEL_AUDIO_DEVCL 0x808629FB
#define INTEL_AUDIO_DEVBLC 0x80862801
#define INTEL_AUDIO_DEVCTG 0x80862802
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index a2716d2..28dcb47 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -194,7 +194,7 @@ static void i915_save_display(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
/* Display arbitration control */
- if (dev_priv->info->gen <= 4)
+ if (dev_priv->info.gen <= 4)
dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
/* This is only meaningful in non-KMS mode */
@@ -260,7 +260,7 @@ static void i915_restore_display(struct drm_device *dev)
u32 mask = 0xffffffff;
/* Display arbitration */
- if (dev_priv->info->gen <= 4)
+ if (dev_priv->info.gen <= 4)
I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
if (!drm_core_check_feature(dev, DRIVER_MODESET))
@@ -271,7 +271,7 @@ static void i915_restore_display(struct drm_device *dev)
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
- else if (dev_priv->info->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
+ else if (dev_priv->info.gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
@@ -324,7 +324,7 @@ int i915_save_state(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
int i;
- if (dev_priv->info->gen <= 4)
+ if (dev_priv->info.gen <= 4)
pci_read_config_byte(dev->pdev, LBB,
&dev_priv->regfile.saveLBB);
@@ -353,7 +353,7 @@ int i915_save_state(struct drm_device *dev)
intel_disable_gt_powersave(dev);
/* Cache mode state */
- if (dev_priv->info->gen < 7)
+ if (dev_priv->info.gen < 7)
dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
/* Memory Arbitration state */
@@ -377,7 +377,7 @@ int i915_restore_state(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
int i;
- if (dev_priv->info->gen <= 4)
+ if (dev_priv->info.gen <= 4)
pci_write_config_byte(dev->pdev, LBB,
dev_priv->regfile.saveLBB);
@@ -403,7 +403,7 @@ int i915_restore_state(struct drm_device *dev)
}
/* Cache mode state */
- if (dev_priv->info->gen < 7)
+ if (dev_priv->info.gen < 7)
I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
0xffff0000);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index bccc52f..e1bdce9 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -562,7 +562,7 @@ void i915_setup_sysfs(struct drm_device *dev)
int ret;
#ifdef CONFIG_PM
- if (dev_priv->info->gen >= 6) {
+ if (dev_priv->info.gen >= 6) {
ret = sysfs_merge_group(&dev->primary->kdev->kobj,
&rc6_attr_group);
if (ret)
@@ -585,7 +585,7 @@ void i915_setup_sysfs(struct drm_device *dev)
ret = 0;
if (IS_VALLEYVIEW(dev))
ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs);
- else if (dev_priv->info->gen >= 6)
+ else if (dev_priv->info.gen >= 6)
ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs);
if (ret)
DRM_ERROR("RPS sysfs setup failed\n");
diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c
index 08b588e..9b1c6d8 100644
--- a/drivers/gpu/drm/i915/i915_ums.c
+++ b/drivers/gpu/drm/i915/i915_ums.c
@@ -124,7 +124,7 @@ void i915_save_display_reg(struct drm_device *dev)
dev_priv->regfile.saveFPA1 = I915_READ(_FPA1);
dev_priv->regfile.saveDPLL_A = I915_READ(_DPLL_A);
}
- if (dev_priv->info->gen >= 4 && !HAS_PCH_SPLIT(dev))
+ if (dev_priv->info.gen >= 4 && !HAS_PCH_SPLIT(dev))
dev_priv->regfile.saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
dev_priv->regfile.saveHTOTAL_A = I915_READ(_HTOTAL_A);
dev_priv->regfile.saveHBLANK_A = I915_READ(_HBLANK_A);
@@ -162,7 +162,7 @@ void i915_save_display_reg(struct drm_device *dev)
dev_priv->regfile.saveDSPASIZE = I915_READ(_DSPASIZE);
dev_priv->regfile.saveDSPAPOS = I915_READ(_DSPAPOS);
dev_priv->regfile.saveDSPAADDR = I915_READ(_DSPAADDR);
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
dev_priv->regfile.saveDSPASURF = I915_READ(_DSPASURF);
dev_priv->regfile.saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
}
@@ -181,7 +181,7 @@ void i915_save_display_reg(struct drm_device *dev)
dev_priv->regfile.saveFPB1 = I915_READ(_FPB1);
dev_priv->regfile.saveDPLL_B = I915_READ(_DPLL_B);
}
- if (dev_priv->info->gen >= 4 && !HAS_PCH_SPLIT(dev))
+ if (dev_priv->info.gen >= 4 && !HAS_PCH_SPLIT(dev))
dev_priv->regfile.saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
dev_priv->regfile.saveHTOTAL_B = I915_READ(_HTOTAL_B);
dev_priv->regfile.saveHBLANK_B = I915_READ(_HBLANK_B);
@@ -219,7 +219,7 @@ void i915_save_display_reg(struct drm_device *dev)
dev_priv->regfile.saveDSPBSIZE = I915_READ(_DSPBSIZE);
dev_priv->regfile.saveDSPBPOS = I915_READ(_DSPBPOS);
dev_priv->regfile.saveDSPBADDR = I915_READ(_DSPBADDR);
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
dev_priv->regfile.saveDSPBSURF = I915_READ(_DSPBSURF);
dev_priv->regfile.saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
}
@@ -227,7 +227,7 @@ void i915_save_display_reg(struct drm_device *dev)
dev_priv->regfile.savePIPEBSTAT = I915_READ(_PIPEBSTAT);
/* Fences */
- switch (dev_priv->info->gen) {
+ switch (dev_priv->info.gen) {
case 7:
case 6:
for (i = 0; i < 16; i++)
@@ -278,7 +278,7 @@ void i915_save_display_reg(struct drm_device *dev)
dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
} else {
dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
- if (dev_priv->info->gen >= 4)
+ if (dev_priv->info.gen >= 4)
dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
}
@@ -302,7 +302,7 @@ void i915_restore_display_reg(struct drm_device *dev)
I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
} else {
- if (dev_priv->info->gen >= 4)
+ if (dev_priv->info.gen >= 4)
I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
}
@@ -320,7 +320,7 @@ void i915_restore_display_reg(struct drm_device *dev)
}
/* Fences */
- switch (dev_priv->info->gen) {
+ switch (dev_priv->info.gen) {
case 7:
case 6:
for (i = 0; i < 16; i++)
@@ -377,7 +377,7 @@ void i915_restore_display_reg(struct drm_device *dev)
I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A);
POSTING_READ(dpll_a_reg);
udelay(150);
- if (dev_priv->info->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
+ if (dev_priv->info.gen >= 4 && !HAS_PCH_SPLIT(dev)) {
I915_WRITE(_DPLL_A_MD, dev_priv->regfile.saveDPLL_A_MD);
POSTING_READ(_DPLL_A_MD);
}
@@ -421,7 +421,7 @@ void i915_restore_display_reg(struct drm_device *dev)
I915_WRITE(_PIPEASRC, dev_priv->regfile.savePIPEASRC);
I915_WRITE(_DSPAADDR, dev_priv->regfile.saveDSPAADDR);
I915_WRITE(_DSPASTRIDE, dev_priv->regfile.saveDSPASTRIDE);
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
I915_WRITE(_DSPASURF, dev_priv->regfile.saveDSPASURF);
I915_WRITE(_DSPATILEOFF, dev_priv->regfile.saveDSPATILEOFF);
}
@@ -446,7 +446,7 @@ void i915_restore_display_reg(struct drm_device *dev)
I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B);
POSTING_READ(dpll_b_reg);
udelay(150);
- if (dev_priv->info->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
+ if (dev_priv->info.gen >= 4 && !HAS_PCH_SPLIT(dev)) {
I915_WRITE(_DPLL_B_MD, dev_priv->regfile.saveDPLL_B_MD);
POSTING_READ(_DPLL_B_MD);
}
@@ -490,7 +490,7 @@ void i915_restore_display_reg(struct drm_device *dev)
I915_WRITE(_PIPEBSRC, dev_priv->regfile.savePIPEBSRC);
I915_WRITE(_DSPBADDR, dev_priv->regfile.saveDSPBADDR);
I915_WRITE(_DSPBSTRIDE, dev_priv->regfile.saveDSPBSTRIDE);
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
I915_WRITE(_DSPBSURF, dev_priv->regfile.saveDSPBSURF);
I915_WRITE(_DSPBTILEOFF, dev_priv->regfile.saveDSPBTILEOFF);
}
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 4523e51..e3aaac6 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -355,7 +355,7 @@ static int intel_bios_ssc_frequency(struct drm_device *dev,
{
struct drm_i915_private *dev_priv = dev->dev_private;
- switch (dev_priv->info->gen) {
+ switch (dev_priv->info.gen) {
case 2:
return alternate ? 66667 : 48000;
case 3:
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 8e66a96..20b5ebd 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -185,7 +185,7 @@ static void intel_crt_dpms(struct drm_connector *connector, int mode)
int old_dpms;
/* PCH platforms and VLV only support on/off. */
- if (dev_priv->info->gen >= 5 && mode != DRM_MODE_DPMS_ON)
+ if (dev_priv->info.gen >= 5 && mode != DRM_MODE_DPMS_ON)
mode = DRM_MODE_DPMS_OFF;
if (mode == connector->dpms)
@@ -276,7 +276,7 @@ static void intel_crt_mode_set(struct intel_encoder *encoder)
struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
u32 adpa;
- if (dev_priv->info->gen >= 5)
+ if (dev_priv->info.gen >= 5)
adpa = ADPA_HOTPLUG_BITS;
else
adpa = 0;
@@ -713,7 +713,7 @@ static void intel_crt_reset(struct drm_connector *connector)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crt *crt = intel_attached_crt(connector);
- if (dev_priv->info->gen >= 5) {
+ if (dev_priv->info.gen >= 5) {
u32 adpa;
adpa = I915_READ(crt->adpa_reg);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ab016f0..6478334 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -778,7 +778,7 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
struct drm_i915_private *dev_priv = dev->dev_private;
int pipestat_reg = PIPESTAT(pipe);
- if (IS_G4X(dev) || dev_priv->info->gen >= 5) {
+ if (IS_G4X(dev) || dev_priv->info.gen >= 5) {
g4x_wait_for_vblank(dev, pipe);
return;
}
@@ -848,7 +848,7 @@ void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
pipe);
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
int reg = PIPECONF(cpu_transcoder);
/* Wait for the Pipe State to go off */
@@ -1030,7 +1030,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
u32 val;
/* ILK FDI PLL is always enabled */
- if (dev_priv->info->gen == 5)
+ if (dev_priv->info.gen == 5)
return;
/* On Haswell, DDI ports are responsible for the FDI PLL setup */
@@ -1160,7 +1160,7 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
int cur_pipe;
/* Primary planes are fixed to pipes on gen4+ */
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
reg = DSPCNTR(pipe);
val = I915_READ(reg);
WARN((val & DISPLAY_PLANE_ENABLE),
@@ -1196,13 +1196,13 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
"sprite %c assertion failure, should be off on pipe %c but is still active\n",
sprite_name(pipe, i), pipe_name(pipe));
}
- } else if (dev_priv->info->gen >= 7) {
+ } else if (dev_priv->info.gen >= 7) {
reg = SPRCTL(pipe);
val = I915_READ(reg);
WARN((val & SPRITE_ENABLE),
"sprite %c assertion failure, should be off on pipe %c but is still active\n",
plane_name(pipe), pipe_name(pipe));
- } else if (dev_priv->info->gen >= 5) {
+ } else if (dev_priv->info.gen >= 5) {
reg = DVSCNTR(pipe);
val = I915_READ(reg);
WARN((val & DVS_ENABLE),
@@ -1442,7 +1442,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
assert_pipe_disabled(dev_priv, crtc->pipe);
/* No really, not for ILK+ */
- BUG_ON(dev_priv->info->gen >= 5);
+ BUG_ON(dev_priv->info.gen >= 5);
/* PLL is protected by panel, make sure we can write it */
if (IS_MOBILE(dev) && !IS_I830(dev))
@@ -1454,7 +1454,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
POSTING_READ(reg);
udelay(150);
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
I915_WRITE(DPLL_MD(crtc->pipe),
crtc->config.dpll_hw_state.dpll_md);
} else {
@@ -1549,7 +1549,7 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
/* PCH PLLs only available on ILK, SNB and IVB */
- BUG_ON(dev_priv->info->gen < 5);
+ BUG_ON(dev_priv->info.gen < 5);
if (WARN_ON(pll == NULL))
return;
@@ -1578,7 +1578,7 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
/* PCH only available on ILK+ */
- BUG_ON(dev_priv->info->gen < 5);
+ BUG_ON(dev_priv->info.gen < 5);
if (WARN_ON(pll == NULL))
return;
@@ -1613,7 +1613,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
uint32_t reg, val, pipeconf_val;
/* PCH only available on ILK+ */
- BUG_ON(dev_priv->info->gen < 5);
+ BUG_ON(dev_priv->info.gen < 5);
/* Make sure PCH DPLL is enabled */
assert_shared_dpll_enabled(dev_priv,
@@ -1666,7 +1666,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
u32 val, pipeconf_val;
/* PCH only available on ILK+ */
- BUG_ON(dev_priv->info->gen < 5);
+ BUG_ON(dev_priv->info.gen < 5);
/* FDI must be feeding us bits for PCH ports */
assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
@@ -1847,7 +1847,7 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
enum plane plane)
{
- u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
+ u32 reg = dev_priv->info.gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
I915_WRITE(reg, I915_READ(reg));
POSTING_READ(reg);
@@ -1921,7 +1921,7 @@ static bool need_vtd_wa(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
#ifdef CONFIG_INTEL_IOMMU
- if (dev_priv->info->gen >= 6 && intel_iommu_gfx_mapped)
+ if (dev_priv->info.gen >= 6 && intel_iommu_gfx_mapped)
return true;
#endif
return false;
@@ -1940,7 +1940,7 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
case I915_TILING_NONE:
if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
alignment = 128 * 1024;
- else if (dev_priv->info->gen >= 4)
+ else if (dev_priv->info.gen >= 4)
alignment = 4 * 1024;
else
alignment = 64 * 1024;
@@ -2083,7 +2083,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
BUG();
}
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
if (obj->tiling_mode != I915_TILING_NONE)
dspcntr |= DISPPLANE_TILED;
else
@@ -2097,7 +2097,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
intel_crtc->dspaddr_offset =
intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
fb->bits_per_pixel / 8,
@@ -2111,7 +2111,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
fb->pitches[0]);
I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
I915_MODIFY_DISPBASE(DSPSURF(plane),
i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
@@ -2340,10 +2340,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
return 0;
}
- if (intel_crtc->plane > dev_priv->info->num_pipes) {
+ if (intel_crtc->plane > dev_priv->info.num_pipes) {
DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
plane_name(intel_crtc->plane),
- dev_priv->info->num_pipes);
+ dev_priv->info.num_pipes);
return -EINVAL;
}
@@ -4472,7 +4472,7 @@ static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
}
}
- if (dev_priv->info->num_pipes == 2)
+ if (dev_priv->info.num_pipes == 2)
return true;
/* Ivybridge 3 pipe is really complicated */
@@ -4568,7 +4568,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
/* FIXME should check pixel clock limits on all platforms */
- if (dev_priv->info->gen < 4) {
+ if (dev_priv->info.gen < 4) {
int clock_limit =
dev_priv->display.get_display_clock_speed(dev);
@@ -4602,13 +4602,13 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
/* Cantiga+ cannot handle modes with a hsync front porch of 0.
* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
*/
- if ((dev_priv->info->gen > 4 || IS_G4X(dev)) &&
+ if ((dev_priv->info.gen > 4 || IS_G4X(dev)) &&
adjusted_mode->hsync_start == adjusted_mode->hdisplay)
return -EINVAL;
if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
- } else if (dev_priv->info->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
+ } else if (dev_priv->info.gen <= 4 && pipe_config->pipe_bpp > 8*3) {
/* only a 8bpc pipe, with 6bpc dither through the panel fitter
* for lvds. */
pipe_config->pipe_bpp = 8*3;
@@ -4876,7 +4876,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
int pipe = crtc->pipe;
enum transcoder transcoder = crtc->config.cpu_transcoder;
- if (dev_priv->info->gen >= 5) {
+ if (dev_priv->info.gen >= 5) {
I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
@@ -5060,7 +5060,7 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
break;
}
- if (dev_priv->info->gen >= 4)
+ if (dev_priv->info.gen >= 4)
dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
if (crtc->config.sdvo_tv_clock)
@@ -5074,7 +5074,7 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
dpll |= DPLL_VCO_ENABLE;
crtc->config.dpll_hw_state.dpll = dpll;
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
u32 dpll_md = (crtc->config.pixel_multiplier - 1)
<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
crtc->config.dpll_hw_state.dpll_md = dpll_md;
@@ -5146,7 +5146,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
vsyncshift = 0;
}
- if (dev_priv->info->gen > 3)
+ if (dev_priv->info.gen > 3)
I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
I915_WRITE(HTOTAL(cpu_transcoder),
@@ -5436,7 +5436,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
return;
/* Check whether the pfit is attached to our pipe. */
- if (dev_priv->info->gen < 4) {
+ if (dev_priv->info.gen < 4) {
if (crtc->pipe != PIPE_B)
return;
} else {
@@ -5446,7 +5446,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
pipe_config->gmch_pfit.control = tmp;
pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
- if (dev_priv->info->gen < 5)
+ if (dev_priv->info.gen < 5)
pipe_config->gmch_pfit.lvds_border_bits =
I915_READ(LVDS) & LVDS_BORDER_ENABLE;
}
@@ -5507,14 +5507,14 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
}
}
- if (dev_priv->info->gen < 4)
+ if (dev_priv->info.gen < 4)
pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
intel_get_pipe_timings(crtc, pipe_config);
i9xx_get_pfit_config(crtc, pipe_config);
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
tmp = I915_READ(DPLL_MD(crtc->pipe));
pipe_config->pixel_multiplier =
((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
@@ -6012,7 +6012,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
- if (dev_priv->info->gen > 6) {
+ if (dev_priv->info.gen > 6) {
uint16_t postoff = 0;
if (intel_crtc->config.limited_color_range)
@@ -6360,7 +6360,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = dev->dev_private;
enum pipe pipe = crtc->pipe;
- if (dev_priv->info->gen >= 5) {
+ if (dev_priv->info.gen >= 5) {
m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
@@ -7544,7 +7544,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
/* we only need to pin inside GTT if cursor is non-phy */
mutex_lock(&dev->struct_mutex);
- if (!dev_priv->info->cursor_needs_physical) {
+ if (!dev_priv->info.cursor_needs_physical) {
unsigned alignment;
if (obj->tiling_mode) {
@@ -7592,7 +7592,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
finish:
if (intel_crtc->cursor_bo) {
- if (dev_priv->info->cursor_needs_physical) {
+ if (dev_priv->info.cursor_needs_physical) {
if (intel_crtc->cursor_bo != obj)
i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
} else
@@ -8175,7 +8175,7 @@ void intel_mark_idle(struct drm_device *dev)
intel_decrease_pllclock(crtc);
}
- if (dev_priv->info->gen >= 6)
+ if (dev_priv->info.gen >= 6)
gen6_rps_idle(dev->dev_private);
}
@@ -8621,7 +8621,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
* TILEOFF/LINOFF registers can't be changed via MI display flips.
* Note that pitch changes could also affect these register.
*/
- if (dev_priv->info->gen > 3 &&
+ if (dev_priv->info.gen > 3 &&
(fb->offsets[0] != crtc->fb->offsets[0] ||
fb->pitches[0] != crtc->fb->pitches[0]))
return -EINVAL;
@@ -8818,7 +8818,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
case DRM_FORMAT_XRGB1555:
case DRM_FORMAT_ARGB1555:
/* checked in intel_framebuffer_init already */
- if (WARN_ON(dev_priv->info->gen > 3))
+ if (WARN_ON(dev_priv->info.gen > 3))
return -EINVAL;
case DRM_FORMAT_RGB565:
bpp = 6*3; /* min is 18bpp */
@@ -8826,7 +8826,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ABGR8888:
/* checked in intel_framebuffer_init already */
- if (WARN_ON(dev_priv->info->gen < 4))
+ if (WARN_ON(dev_priv->info.gen < 4))
return -EINVAL;
case DRM_FORMAT_XRGB8888:
case DRM_FORMAT_ARGB8888:
@@ -8837,7 +8837,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_ABGR2101010:
/* checked in intel_framebuffer_init already */
- if (WARN_ON(dev_priv->info->gen < 4))
+ if (WARN_ON(dev_priv->info.gen < 4))
return -EINVAL;
bpp = 10*3;
break;
@@ -9331,7 +9331,7 @@ intel_pipe_config_compare(struct drm_device *dev,
PIPE_CONF_CHECK_I(gmch_pfit.control);
/* pfit ratios are autocomputed by the hw on gen4+ */
- if (dev_priv->info->gen < 4)
+ if (dev_priv->info.gen < 4)
PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
PIPE_CONF_CHECK_I(pch_pfit.enabled);
@@ -9350,7 +9350,7 @@ intel_pipe_config_compare(struct drm_device *dev,
PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
- if (IS_G4X(dev) || dev_priv->info->gen >= 5)
+ if (IS_G4X(dev) || dev_priv->info.gen >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
if (!HAS_DDI(dev)) {
@@ -10165,7 +10165,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
*/
intel_crtc->pipe = pipe;
intel_crtc->plane = pipe;
- if (IS_MOBILE(dev) && dev_priv->info->gen < 4) {
+ if (IS_MOBILE(dev) && dev_priv->info.gen < 4) {
DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
intel_crtc->plane = !pipe;
}
@@ -10432,14 +10432,14 @@ int intel_framebuffer_init(struct drm_device *dev,
return -EINVAL;
}
- if (dev_priv->info->gen >= 5 && !IS_VALLEYVIEW(dev)) {
+ if (dev_priv->info.gen >= 5 && !IS_VALLEYVIEW(dev)) {
pitch_limit = 32*1024;
- } else if (dev_priv->info->gen >= 4) {
+ } else if (dev_priv->info.gen >= 4) {
if (obj->tiling_mode)
pitch_limit = 16*1024;
else
pitch_limit = 32*1024;
- } else if (dev_priv->info->gen >= 3) {
+ } else if (dev_priv->info.gen >= 3) {
if (obj->tiling_mode)
pitch_limit = 8*1024;
else
@@ -10471,7 +10471,7 @@ int intel_framebuffer_init(struct drm_device *dev,
break;
case DRM_FORMAT_XRGB1555:
case DRM_FORMAT_ARGB1555:
- if (dev_priv->info->gen > 3) {
+ if (dev_priv->info.gen > 3) {
DRM_DEBUG("unsupported pixel format: %s\n",
drm_get_format_name(mode_cmd->pixel_format));
return -EINVAL;
@@ -10483,7 +10483,7 @@ int intel_framebuffer_init(struct drm_device *dev,
case DRM_FORMAT_ARGB2101010:
case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_ABGR2101010:
- if (dev_priv->info->gen < 4) {
+ if (dev_priv->info.gen < 4) {
DRM_DEBUG("unsupported pixel format: %s\n",
drm_get_format_name(mode_cmd->pixel_format));
return -EINVAL;
@@ -10493,7 +10493,7 @@ int intel_framebuffer_init(struct drm_device *dev,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_VYUY:
- if (dev_priv->info->gen < 5) {
+ if (dev_priv->info.gen < 5) {
DRM_DEBUG("unsupported pixel format: %s\n",
drm_get_format_name(mode_cmd->pixel_format));
return -EINVAL;
@@ -10658,7 +10658,7 @@ static void intel_init_display(struct drm_device *dev)
/* Default just returns -ENODEV to indicate unsupported */
dev_priv->display.queue_flip = intel_default_queue_flip;
- switch (dev_priv->info->gen) {
+ switch (dev_priv->info.gen) {
case 2:
dev_priv->display.queue_flip = intel_gen2_queue_flip;
break;
@@ -10855,7 +10855,7 @@ void intel_modeset_init(struct drm_device *dev)
intel_init_pm(dev);
- if (dev_priv->info->num_pipes == 0)
+ if (dev_priv->info.num_pipes == 0)
return;
intel_init_display(dev);
@@ -10873,8 +10873,8 @@ void intel_modeset_init(struct drm_device *dev)
dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
DRM_DEBUG_KMS("%d display pipe%s available.\n",
- dev_priv->info->num_pipes,
- dev_priv->info->num_pipes > 1 ? "s" : "");
+ dev_priv->info.num_pipes,
+ dev_priv->info.num_pipes > 1 ? "s" : "");
for_each_pipe(i) {
intel_crtc_init(dev, i);
@@ -10943,7 +10943,7 @@ intel_check_plane_mapping(struct intel_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
u32 reg, val;
- if (dev_priv->info->num_pipes == 1)
+ if (dev_priv->info.num_pipes == 1)
return true;
reg = DSPCNTR(!crtc->plane);
@@ -10969,7 +10969,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
/* We need to sanitize the plane -> pipe mapping first because this will
* disable the crtc (and hence change the state) if it is wrong. Note
* that gen4+ has a fixed plane -> pipe mapping. */
- if (dev_priv->info->gen < 4 && !intel_check_plane_mapping(crtc)) {
+ if (dev_priv->info.gen < 4 && !intel_check_plane_mapping(crtc)) {
struct intel_connector *connector;
bool plane;
@@ -11347,7 +11347,7 @@ void intel_connector_attach_encoder(struct intel_connector *connector,
int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- unsigned reg = dev_priv->info->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
+ unsigned reg = dev_priv->info.gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
u16 gmch_ctrl;
pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl);
@@ -11415,7 +11415,7 @@ intel_display_capture_error_state(struct drm_device *dev)
};
int i;
- if (dev_priv->info->num_pipes == 0)
+ if (dev_priv->info.num_pipes == 0)
return NULL;
error = kzalloc(sizeof(*error), GFP_ATOMIC);
@@ -11431,7 +11431,7 @@ intel_display_capture_error_state(struct drm_device *dev)
if (!error->pipe[i].power_domain_on)
continue;
- if (dev_priv->info->gen <= 6 || IS_VALLEYVIEW(dev)) {
+ if (dev_priv->info.gen <= 6 || IS_VALLEYVIEW(dev)) {
error->cursor[i].control = I915_READ(CURCNTR(i));
error->cursor[i].position = I915_READ(CURPOS(i));
error->cursor[i].base = I915_READ(CURBASE(i));
@@ -11443,13 +11443,13 @@ intel_display_capture_error_state(struct drm_device *dev)
error->plane[i].control = I915_READ(DSPCNTR(i));
error->plane[i].stride = I915_READ(DSPSTRIDE(i));
- if (dev_priv->info->gen <= 3) {
+ if (dev_priv->info.gen <= 3) {
error->plane[i].size = I915_READ(DSPSIZE(i));
error->plane[i].pos = I915_READ(DSPPOS(i));
}
- if (dev_priv->info->gen <= 7 && !IS_HASWELL(dev))
+ if (dev_priv->info.gen <= 7 && !IS_HASWELL(dev))
error->plane[i].addr = I915_READ(DSPADDR(i));
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
error->plane[i].surface = I915_READ(DSPSURF(i));
error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
}
@@ -11457,7 +11457,7 @@ intel_display_capture_error_state(struct drm_device *dev)
error->pipe[i].source = I915_READ(PIPESRC(i));
}
- error->num_transcoders = dev_priv->info->num_pipes;
+ error->num_transcoders = dev_priv->info.num_pipes;
if (HAS_DDI(dev_priv->dev))
error->num_transcoders++; /* Account for eDP. */
@@ -11496,7 +11496,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
if (!error)
return;
- err_printf(m, "Num Pipes: %d\n", dev_priv->info->num_pipes);
+ err_printf(m, "Num Pipes: %d\n", dev_priv->info.num_pipes);
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
err_printf(m, "PWR_WELL_CTL2: %08x\n",
error->power_well_driver);
@@ -11509,13 +11509,13 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
err_printf(m, "Plane [%d]:\n", i);
err_printf(m, " CNTR: %08x\n", error->plane[i].control);
err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
- if (dev_priv->info->gen <= 3) {
+ if (dev_priv->info.gen <= 3) {
err_printf(m, " SIZE: %08x\n", error->plane[i].size);
err_printf(m, " POS: %08x\n", error->plane[i].pos);
}
- if (dev_priv->info->gen <= 7 && !IS_HASWELL(dev))
+ if (dev_priv->info.gen <= 7 && !IS_HASWELL(dev))
err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
err_printf(m, " SURF: %08x\n", error->plane[i].surface);
err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
}
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 6e8adc3..f44a4c6 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -276,7 +276,7 @@ int intel_fbdev_init(struct drm_device *dev)
ifbdev->helper.funcs = &intel_fb_helper_funcs;
ret = drm_fb_helper_init(dev, &ifbdev->helper,
- dev_priv->info->num_pipes,
+ dev_priv->info.num_pipes,
4);
if (ret) {
kfree(ifbdev);
@@ -341,7 +341,7 @@ void intel_fbdev_restore_mode(struct drm_device *dev)
int ret;
struct drm_i915_private *dev_priv = dev->dev_private;
- if (dev_priv->info->num_pipes == 0)
+ if (dev_priv->info.num_pipes == 0)
return;
drm_modeset_lock_all(dev);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 1243af0..0eec394 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -848,7 +848,7 @@ static int hdmi_portclock_limit(struct intel_hdmi *hdmi)
if (IS_G4X(dev))
return 165000;
- else if (IS_HASWELL(dev) || dev_priv->info->gen >= 8)
+ else if (IS_HASWELL(dev) || dev_priv->info.gen >= 8)
return 300000;
else
return 225000;
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index e97b563..3e1e819 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -264,7 +264,7 @@ intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
* shared with another device. The kernel then disables that interrupt source
* and so prevents the other device from working properly.
*/
-#define HAS_GMBUS_IRQ(dev) (dev_priv->info->gen >= 5)
+#define HAS_GMBUS_IRQ(dev) (dev_priv->info.gen >= 5)
static int
gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
u32 gmbus2_status,
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 2cd7315..994364d 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -112,7 +112,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
pipe_config->adjusted_mode.flags |= flags;
/* gen2/3 store dither state in pfit control, needs to match */
- if (dev_priv->info->gen < 4) {
+ if (dev_priv->info.gen < 4) {
tmp = I915_READ(PFIT_CONTROL);
pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
@@ -182,7 +182,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
/* Set the dithering flag on LVDS as needed, note that there is no
* special lvds dither control bit on pch-split platforms, dithering is
* only controlled through the PIPECONF reg. */
- if (dev_priv->info->gen == 4) {
+ if (dev_priv->info.gen == 4) {
/* Bspec wording suggests that LVDS port dithering only exists
* for 18bpp panels. */
if (crtc->config.dither && crtc->config.pipe_bpp == 18)
@@ -285,7 +285,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
unsigned int lvds_bpp;
/* Should never happen!! */
- if (dev_priv->info->gen < 4 && intel_crtc->pipe == 0) {
+ if (dev_priv->info.gen < 4 && intel_crtc->pipe == 0) {
DRM_ERROR("Can't support LVDS on pipe A\n");
return false;
}
@@ -877,7 +877,7 @@ static bool intel_lvds_supported(struct drm_device *dev)
/* Otherwise LVDS was only attached to mobile products,
* except for the inglorious 830gm */
- if (dev_priv->info->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
+ if (dev_priv->info.gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
return true;
return false;
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 2e0b899..70f029e 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -841,7 +841,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
/* XXX: This is not the same logic as in the xorg driver, but more in
* line with the intel documentation for the i965
*/
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
/* on i965 use the PGM reg to read out the autoscaler values */
ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
} else {
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index c3ceb84..beb45ea 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -277,7 +277,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
break;
case DRM_MODE_SCALE_ASPECT:
/* Scale but preserve the aspect ratio */
- if (dev_priv->info->gen >= 4)
+ if (dev_priv->info.gen >= 4)
i965_scale_aspect(pipe_config, &pfit_control);
else
i9xx_scale_aspect(pipe_config, &pfit_control,
@@ -291,7 +291,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
if (pipe_config->pipe_src_h != adjusted_mode->vdisplay ||
pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
pfit_control |= PFIT_ENABLE;
- if (dev_priv->info->gen >= 4)
+ if (dev_priv->info.gen >= 4)
pfit_control |= PFIT_SCALING_AUTO;
else
pfit_control |= (VERT_AUTO_SCALE |
@@ -307,7 +307,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
/* 965+ wants fuzzy fitting */
/* FIXME: handle multiple panels by failing gracefully */
- if (dev_priv->info->gen >= 4)
+ if (dev_priv->info.gen >= 4)
pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
PFIT_FILTER_FUZZY);
@@ -318,7 +318,7 @@ out:
}
/* Make sure pre-965 set dither correctly for 18bpp panels. */
- if (dev_priv->info->gen < 4 && pipe_config->pipe_bpp == 18)
+ if (dev_priv->info.gen < 4 && pipe_config->pipe_bpp == 18)
pfit_control |= PANEL_8TO6_DITHER_ENABLE;
pipe_config->gmch_pfit.control = pfit_control;
@@ -377,7 +377,7 @@ static u32 i9xx_get_backlight(struct intel_connector *connector)
u32 val;
val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
- if (dev_priv->info->gen < 4)
+ if (dev_priv->info.gen < 4)
val >>= 1;
if (panel->backlight.combination_mode) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f018d24..3160ffb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -506,7 +506,7 @@ void intel_update_fbc(struct drm_device *dev)
adjusted_mode = &intel_crtc->config.adjusted_mode;
if (i915_enable_fbc < 0 &&
- dev_priv->info->gen <= 7 && !IS_HASWELL(dev)) {
+ dev_priv->info.gen <= 7 && !IS_HASWELL(dev)) {
if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
DRM_DEBUG_KMS("disabled per chip default\n");
goto out_disable;
@@ -524,7 +524,7 @@ void intel_update_fbc(struct drm_device *dev)
goto out_disable;
}
- if (IS_G4X(dev) || dev_priv->info->gen >= 5) {
+ if (IS_G4X(dev) || dev_priv->info.gen >= 5) {
max_width = 4096;
max_height = 2048;
} else {
@@ -537,7 +537,7 @@ void intel_update_fbc(struct drm_device *dev)
DRM_DEBUG_KMS("mode too large for compression, disabling\n");
goto out_disable;
}
- if ((dev_priv->info->gen < 4 || IS_HASWELL(dev)) &&
+ if ((dev_priv->info.gen < 4 || IS_HASWELL(dev)) &&
intel_crtc->plane != PLANE_A) {
if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
DRM_DEBUG_KMS("plane not A, disabling compression\n");
@@ -1823,9 +1823,9 @@ static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
static unsigned int
ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
{
- if (dev_priv->info->gen >= 8)
+ if (dev_priv->info.gen >= 8)
return 3072;
- else if (dev_priv->info->gen >= 7)
+ else if (dev_priv->info.gen >= 7)
return 768;
else
return 512;
@@ -1847,14 +1847,14 @@ static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
/* HSW allows LP1+ watermarks even with multiple pipes */
if (level == 0 || config->num_pipes_active > 1) {
- fifo_size /= dev_priv->info->num_pipes;
+ fifo_size /= dev_priv->info.num_pipes;
/*
* For some reason the non self refresh
* FIFO size is only half of the self
* refresh FIFO size on ILK/SNB.
*/
- if (dev_priv->info->gen <= 6)
+ if (dev_priv->info.gen <= 6)
fifo_size /= 2;
}
@@ -1870,9 +1870,9 @@ static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
}
/* clamp to max that the registers can hold */
- if (dev_priv->info->gen >= 8)
+ if (dev_priv->info.gen >= 8)
max = level == 0 ? 255 : 2047;
- else if (dev_priv->info->gen >= 7)
+ else if (dev_priv->info.gen >= 7)
/* IVB/HSW primary/sprite plane watermarks */
max = level == 0 ? 127 : 1023;
else if (!is_sprite)
@@ -1895,7 +1895,7 @@ static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
return 64;
/* otherwise just report max that registers can hold */
- if (dev_priv->info->gen >= 7)
+ if (dev_priv->info.gen >= 7)
return level == 0 ? 63 : 255;
else
return level == 0 ? 31 : 63;
@@ -1905,7 +1905,7 @@ static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
static unsigned int ilk_fbc_wm_max(const struct drm_i915_private *dev_priv)
{
/* max that registers can hold */
- if (dev_priv->info->gen >= 8)
+ if (dev_priv->info.gen >= 8)
return 31;
else
return 15;
@@ -2024,14 +2024,14 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
wm[2] = (sskpd >> 12) & 0xFF;
wm[3] = (sskpd >> 20) & 0x1FF;
wm[4] = (sskpd >> 32) & 0x1FF;
- } else if (dev_priv->info->gen >= 6) {
+ } else if (dev_priv->info.gen >= 6) {
uint32_t sskpd = I915_READ(MCH_SSKPD);
wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
- } else if (dev_priv->info->gen >= 5) {
+ } else if (dev_priv->info.gen >= 5) {
uint32_t mltr = I915_READ(MLTR_ILK);
/* ILK primary LP0 latency is 700 ns */
@@ -2045,7 +2045,7 @@ static void
intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv, uint16_t wm[5])
{
/* ILK sprite LP0 latency is 1300 ns */
- if (dev_priv->info->gen == 5)
+ if (dev_priv->info.gen == 5)
wm[0] = 13;
}
@@ -2054,7 +2054,7 @@ static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
struct drm_i915_private *dev_priv = dev->dev_private;
/* ILK cursor LP0 latency is 1300 ns */
- if (dev_priv->info->gen == 5)
+ if (dev_priv->info.gen == 5)
wm[0] = 13;
/* WaDoubleCursorLP3Latency:ivb */
@@ -2069,7 +2069,7 @@ static int ilk_wm_max_level(const struct drm_device *dev)
/* how many WM levels are we expecting */
if (IS_HASWELL(dev))
return 4;
- else if (dev_priv->info->gen >= 6)
+ else if (dev_priv->info.gen >= 6)
return 3;
else
return 2;
@@ -2175,7 +2175,7 @@ static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
ilk_compute_wm_maximums(dev_priv, 0, &config, INTEL_DDB_PART_1_2, &max);
/* ILK/SNB: LP2+ watermarks only w/o sprites */
- if (dev_priv->info->gen <= 6 && params->spr.enabled)
+ if (dev_priv->info.gen <= 6 && params->spr.enabled)
max_level = 1;
/* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
@@ -2230,12 +2230,12 @@ static void ilk_wm_merge(struct drm_device *dev,
int level, max_level = ilk_wm_max_level(dev);
/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
- if ((dev_priv->info->gen <= 6 || IS_IVYBRIDGE(dev)) &&
+ if ((dev_priv->info.gen <= 6 || IS_IVYBRIDGE(dev)) &&
config->num_pipes_active > 1)
return;
/* ILK: FBC WM must be disabled always */
- merged->fbc_wm_enabled = dev_priv->info->gen >= 6;
+ merged->fbc_wm_enabled = dev_priv->info.gen >= 6;
/* merge each WM1+ level */
for (level = 1; level <= max_level; level++) {
@@ -2315,14 +2315,14 @@ static void ilk_compute_wm_results(struct drm_device *dev,
(r->pri_val << WM1_LP_SR_SHIFT) |
r->cur_val;
- if (dev_priv->info->gen >= 8)
+ if (dev_priv->info.gen >= 8)
results->wm_lp[wm_lp - 1] |=
r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
else
results->wm_lp[wm_lp - 1] |=
r->fbc_val << WM1_LP_FBC_SHIFT;
- if (dev_priv->info->gen <= 6 && r->spr_val) {
+ if (dev_priv->info.gen <= 6 && r->spr_val) {
WARN_ON(wm_lp != 1);
results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
} else
@@ -2528,7 +2528,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
previous->wm_lp_spr[0] != results->wm_lp_spr[0])
I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
- if (dev_priv->info->gen >= 7) {
+ if (dev_priv->info.gen >= 7) {
if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
@@ -2578,7 +2578,7 @@ static void ilk_update_wm(struct drm_crtc *crtc)
ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
/* 5/6 split only in single pipe config on IVB+ */
- if (dev_priv->info->gen >= 7 &&
+ if (dev_priv->info.gen >= 7 &&
config.num_pipes_active == 1 && config.sprites_enabled) {
ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_5_6, &max);
ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
@@ -3172,7 +3172,7 @@ int intel_enable_rc6(const struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
/* No RC6 before Ironlake */
- if (dev_priv->info->gen < 5)
+ if (dev_priv->info.gen < 5)
return 0;
/* Respect the kernel parameter if it is set */
@@ -3180,14 +3180,14 @@ int intel_enable_rc6(const struct drm_device *dev)
return i915_enable_rc6;
/* Disable RC6 on Ironlake */
- if (dev_priv->info->gen == 5)
+ if (dev_priv->info.gen == 5)
return 0;
if (IS_HASWELL(dev))
return INTEL_RC6_ENABLE;
/* snb/ivb have more than one rc6 state. */
- if (dev_priv->info->gen == 6)
+ if (dev_priv->info.gen == 6)
return INTEL_RC6_ENABLE;
return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
@@ -3210,7 +3210,7 @@ static void gen6_enable_rps_interrupts(struct drm_device *dev)
/* IVB and SNB hard hangs on looping batchbuffer
* if GEN6_PM_UP_EI_EXPIRED is masked.
*/
- if (dev_priv->info->gen <= 7 && !IS_HASWELL(dev))
+ if (dev_priv->info.gen <= 7 && !IS_HASWELL(dev))
enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
@@ -3450,7 +3450,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
int diff = dev_priv->rps.max_delay - gpu_freq;
unsigned int ia_freq = 0, ring_freq = 0;
- if (dev_priv->info->gen >= 8) {
+ if (dev_priv->info.gen >= 8) {
/* max(2 * GT, DDR). NB: GT is 50MHz units */
ring_freq = max(min_ring_freq, gpu_freq);
} else if (IS_HASWELL(dev)) {
@@ -3850,7 +3850,7 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
{
unsigned long val;
- if (dev_priv->info->gen != 5)
+ if (dev_priv->info.gen != 5)
return 0;
spin_lock_irq(&mchdev_lock);
@@ -4012,7 +4012,7 @@ static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
{ 16000, 14875, },
{ 16125, 15000, },
};
- if (dev_priv->info->is_mobile)
+ if (dev_priv->info.is_mobile)
return v_table[pxvid].vm;
else
return v_table[pxvid].vd;
@@ -4055,7 +4055,7 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
void i915_update_gfx_val(struct drm_i915_private *dev_priv)
{
- if (dev_priv->info->gen != 5)
+ if (dev_priv->info.gen != 5)
return;
spin_lock_irq(&mchdev_lock);
@@ -4106,7 +4106,7 @@ unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
{
unsigned long val;
- if (dev_priv->info->gen != 5)
+ if (dev_priv->info.gen != 5)
return 0;
spin_lock_irq(&mchdev_lock);
@@ -4376,7 +4376,7 @@ void intel_disable_gt_powersave(struct drm_device *dev)
if (IS_IRONLAKE_M(dev)) {
ironlake_disable_drps(dev);
ironlake_disable_rc6(dev);
- } else if (dev_priv->info->gen >= 6) {
+ } else if (dev_priv->info.gen >= 6) {
cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
cancel_work_sync(&dev_priv->rps.work);
mutex_lock(&dev_priv->rps.hw_lock);
@@ -5553,11 +5553,11 @@ void intel_init_pm(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
if (I915_HAS_FBC(dev)) {
- if (dev_priv->info->gen >= 7) {
+ if (dev_priv->info.gen >= 7) {
dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
dev_priv->display.enable_fbc = gen7_enable_fbc;
dev_priv->display.disable_fbc = ironlake_disable_fbc;
- } else if (dev_priv->info->gen >= 5) {
+ } else if (dev_priv->info.gen >= 5) {
dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
dev_priv->display.enable_fbc = ironlake_enable_fbc;
dev_priv->display.disable_fbc = ironlake_disable_fbc;
@@ -5637,7 +5637,7 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.update_wm = NULL;
}
dev_priv->display.init_clock_gating = haswell_init_clock_gating;
- } else if (dev_priv->info->gen == 8) {
+ } else if (dev_priv->info.gen == 8) {
dev_priv->display.init_clock_gating = gen8_init_clock_gating;
} else
dev_priv->display.update_wm = NULL;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1ac11a9..3570dd9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -413,7 +413,7 @@ static void ring_write_tail(struct intel_ring_buffer *ring,
u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
{
drm_i915_private_t *dev_priv = ring->dev->dev_private;
- u32 acthd_reg = dev_priv->info->gen >= 4 ?
+ u32 acthd_reg = dev_priv->info.gen >= 4 ?
RING_ACTHD(ring->mmio_base) : ACTHD;
return I915_READ(acthd_reg);
@@ -425,7 +425,7 @@ static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
u32 addr;
addr = dev_priv->status_page_dmah->busaddr;
- if (dev_priv->info->gen >= 4)
+ if (dev_priv->info.gen >= 4)
addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
I915_WRITE(HWS_PGA, addr);
}
@@ -562,7 +562,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
struct drm_i915_private *dev_priv = dev->dev_private;
int ret = init_ring_common(ring);
- if (dev_priv->info->gen > 3)
+ if (dev_priv->info.gen > 3)
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
/* We need to disable the AsyncFlip performance optimisations in order
@@ -571,11 +571,11 @@ static int init_render_ring(struct intel_ring_buffer *ring)
*
* WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
*/
- if (dev_priv->info->gen >= 6)
+ if (dev_priv->info.gen >= 6)
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
/* Required for the hardware to program scanline values for waiting */
- if (dev_priv->info->gen == 6)
+ if (dev_priv->info.gen == 6)
I915_WRITE(GFX_MODE,
_MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
@@ -584,7 +584,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
_MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
_MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
- if (dev_priv->info->gen >= 5) {
+ if (dev_priv->info.gen >= 5) {
ret = init_pipe_control(ring);
if (ret)
return ret;
@@ -607,7 +607,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
!!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
}
- if (dev_priv->info->gen >= 6)
+ if (dev_priv->info.gen >= 6)
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
if (HAS_L3_DPF(dev))
@@ -623,7 +623,7 @@ static void render_ring_cleanup(struct intel_ring_buffer *ring)
if (ring->scratch.obj == NULL)
return;
- if (dev_priv->info->gen >= 5) {
+ if (dev_priv->info.gen >= 5) {
kunmap(sg_page(ring->scratch.obj->pages->sgl));
i915_gem_object_ggtt_unpin(ring->scratch.obj);
}
@@ -976,7 +976,7 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
POSTING_READ(mmio);
/* Flush the TLB for this page */
- if (dev_priv->info->gen >= 6) {
+ if (dev_priv->info.gen >= 6) {
u32 reg = RING_INSTPM(ring->mmio_base);
I915_WRITE(reg,
_MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
@@ -1653,7 +1653,7 @@ void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
BUG_ON(ring->outstanding_lazy_seqno);
- if (dev_priv->info->gen >= 6) {
+ if (dev_priv->info.gen >= 6) {
I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
if (HAS_VEBOX(ring->dev))
@@ -1709,7 +1709,7 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
return ret;
cmd = MI_FLUSH_DW;
- if (dev_priv->info->gen >= 8)
+ if (dev_priv->info.gen >= 8)
cmd += 1;
/*
* Bspec vol 1c.5 - video engine command streamer:
@@ -1722,7 +1722,7 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
intel_ring_emit(ring, cmd);
intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
- if (dev_priv->info->gen >= 8) {
+ if (dev_priv->info.gen >= 8) {
intel_ring_emit(ring, 0); /* upper addr */
intel_ring_emit(ring, 0); /* value */
} else {
@@ -1814,7 +1814,7 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
return ret;
cmd = MI_FLUSH_DW;
- if (dev_priv->info->gen >= 8)
+ if (dev_priv->info.gen >= 8)
cmd += 1;
/*
* Bspec vol 1c.3 - blitter engine command streamer:
@@ -1827,7 +1827,7 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
MI_FLUSH_DW_OP_STOREDW;
intel_ring_emit(ring, cmd);
intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
- if (dev_priv->info->gen >= 8) {
+ if (dev_priv->info.gen >= 8) {
intel_ring_emit(ring, 0); /* upper addr */
intel_ring_emit(ring, 0); /* value */
} else {
@@ -1851,12 +1851,12 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->id = RCS;
ring->mmio_base = RENDER_RING_BASE;
- if (dev_priv->info->gen >= 6) {
+ if (dev_priv->info.gen >= 6) {
ring->add_request = gen6_add_request;
ring->flush = gen7_render_ring_flush;
- if (dev_priv->info->gen == 6)
+ if (dev_priv->info.gen == 6)
ring->flush = gen6_render_ring_flush;
- if (dev_priv->info->gen >= 8) {
+ if (dev_priv->info.gen >= 8) {
ring->flush = gen8_render_ring_flush;
ring->irq_get = gen8_ring_get_irq;
ring->irq_put = gen8_ring_put_irq;
@@ -1887,7 +1887,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
} else {
ring->add_request = i9xx_add_request;
- if (dev_priv->info->gen < 4)
+ if (dev_priv->info.gen < 4)
ring->flush = gen2_render_ring_flush;
else
ring->flush = gen4_render_ring_flush;
@@ -1907,9 +1907,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
else if (IS_GEN8(dev))
ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
- else if (dev_priv->info->gen >= 6)
+ else if (dev_priv->info.gen >= 6)
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
- else if (dev_priv->info->gen >= 4)
+ else if (dev_priv->info.gen >= 4)
ring->dispatch_execbuffer = i965_dispatch_execbuffer;
else if (IS_I830(dev) || IS_845G(dev))
ring->dispatch_execbuffer = i830_dispatch_execbuffer;
@@ -1953,7 +1953,7 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
ring->id = RCS;
ring->mmio_base = RENDER_RING_BASE;
- if (dev_priv->info->gen >= 6) {
+ if (dev_priv->info.gen >= 6) {
/* non-kms not supported on gen6+ */
return -ENODEV;
}
@@ -1962,7 +1962,7 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
* gem_init ioctl returns with -ENODEV). Hence we do not need to set up
* the special gen5 functions. */
ring->add_request = i9xx_add_request;
- if (dev_priv->info->gen < 4)
+ if (dev_priv->info.gen < 4)
ring->flush = gen2_render_ring_flush;
else
ring->flush = gen4_render_ring_flush;
@@ -1977,7 +1977,7 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
}
ring->irq_enable_mask = I915_USER_INTERRUPT;
ring->write_tail = ring_write_tail;
- if (dev_priv->info->gen >= 4)
+ if (dev_priv->info.gen >= 4)
ring->dispatch_execbuffer = i965_dispatch_execbuffer;
else if (IS_I830(dev) || IS_845G(dev))
ring->dispatch_execbuffer = i830_dispatch_execbuffer;
@@ -2020,7 +2020,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring->id = VCS;
ring->write_tail = ring_write_tail;
- if (dev_priv->info->gen >= 6) {
+ if (dev_priv->info.gen >= 6) {
ring->mmio_base = GEN6_BSD_RING_BASE;
/* gen6 bsd needs a special wa for tail updates */
if (IS_GEN6(dev))
@@ -2029,7 +2029,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring->add_request = gen6_add_request;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
- if (dev_priv->info->gen >= 8) {
+ if (dev_priv->info.gen >= 8) {
ring->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
ring->irq_get = gen8_ring_get_irq;
@@ -2088,7 +2088,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
ring->add_request = gen6_add_request;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
- if (dev_priv->info->gen >= 8) {
+ if (dev_priv->info.gen >= 8) {
ring->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
ring->irq_get = gen8_ring_get_irq;
@@ -2129,7 +2129,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
- if (dev_priv->info->gen >= 8) {
+ if (dev_priv->info.gen >= 8) {
ring->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
ring->irq_get = gen8_ring_get_irq;
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 4e44733..008878d 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1254,13 +1254,13 @@ static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
return;
/* Set the SDVO control regs. */
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
/* The real mode polarity is set by the SDVO commands, using
* struct intel_sdvo_dtd. */
sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
sdvox |= intel_sdvo->color_range;
- if (dev_priv->info->gen < 5)
+ if (dev_priv->info.gen < 5)
sdvox |= SDVO_BORDER_ENABLE;
} else {
sdvox = I915_READ(intel_sdvo->sdvo_reg);
@@ -1283,7 +1283,7 @@ static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
if (intel_sdvo->has_hdmi_audio)
sdvox |= SDVO_AUDIO_ENABLE;
- if (dev_priv->info->gen >= 4) {
+ if (dev_priv->info.gen >= 4) {
/* done in crtc_mode_set as the dpll_md reg must be written early */
} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
/* done in crtc_mode_set as it lives inside the dpll register */
@@ -1293,7 +1293,7 @@ static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
}
if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
- dev_priv->info->gen < 5)
+ dev_priv->info.gen < 5)
sdvox |= SDVO_STALL_SELECT;
intel_sdvo_write_sdvox(intel_sdvo, sdvox);
}
@@ -2410,7 +2410,7 @@ intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
struct drm_i915_private *dev_priv = dev->dev_private;
intel_attach_force_audio_property(&connector->base.base);
- if (dev_priv->info->gen >= 4 && IS_MOBILE(dev)) {
+ if (dev_priv->info.gen >= 4 && IS_MOBILE(dev)) {
intel_attach_broadcast_rgb_property(&connector->base.base);
intel_sdvo->color_range_auto = true;
}
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 5584cd9..7fd1cb2 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1080,14 +1080,14 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
int num_plane_formats;
int ret;
- if (dev_priv->info->gen < 5)
+ if (dev_priv->info.gen < 5)
return -ENODEV;
intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
if (!intel_plane)
return -ENOMEM;
- switch (dev_priv->info->gen) {
+ switch (dev_priv->info.gen) {
case 5:
case 6:
intel_plane->can_scale = true;
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 0448f0b..460ac9e 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1083,7 +1083,7 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
color_conversion->av);
}
- if (dev_priv->info->gen >= 4)
+ if (dev_priv->info.gen >= 4)
I915_WRITE(TV_CLR_KNOBS, 0x00404000);
else
I915_WRITE(TV_CLR_KNOBS, 0x00606000);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 3283059f..22ada66 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -114,7 +114,7 @@ static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
/* WaRsForcewakeWaitTC0:ivb,hsw */
- if (dev_priv->info->gen < 8)
+ if (dev_priv->info.gen < 8)
__gen6_gt_wait_for_thread_c0(dev_priv);
}
@@ -307,7 +307,7 @@ static void intel_uncore_forcewake_reset(struct drm_device *dev)
if (IS_VALLEYVIEW(dev)) {
vlv_force_wake_reset(dev_priv);
- } else if (dev_priv->info->gen >= 6) {
+ } else if (dev_priv->info.gen >= 6) {
__gen6_gt_force_wake_reset(dev_priv);
if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
__gen6_gt_force_wake_mt_reset(dev_priv);
@@ -728,7 +728,7 @@ void intel_uncore_init(struct drm_device *dev)
__gen6_gt_force_wake_put;
}
- switch (dev_priv->info->gen) {
+ switch (dev_priv->info.gen) {
default:
dev_priv->uncore.funcs.mmio_writeb = gen8_write8;
dev_priv->uncore.funcs.mmio_writew = gen8_write16;
@@ -818,7 +818,7 @@ int i915_reg_read_ioctl(struct drm_device *dev,
for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
if (entry->offset == reg->offset &&
- (1 << dev_priv->info->gen & entry->gen_bitmask))
+ (1 << dev_priv->info.gen & entry->gen_bitmask))
break;
}
@@ -983,7 +983,7 @@ int intel_gpu_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- switch (dev_priv->info->gen) {
+ switch (dev_priv->info.gen) {
case 8:
case 7:
case 6: return gen6_do_reset(dev);
--
1.8.3.1
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