On Mon, Dec 16, 2013 at 04:34:26PM -0800, Jesse Barnes wrote:
> + if (INTEL_INFO(dev)->gen >= 4) {
> + if (plane_config->tiled)
> + offset = I915_READ(DSPTILEOFF(plane));
> + else
> + offset = I915_READ(DSPLINOFF(plane));
> + base = I915_READ(DSPSURF(plane)) & 0xfffff000;
> + } else {
> + base = I915_READ(DSPADDR(plane));
> + }
> +
> + val = I915_READ(PIPESRC(pipe));
> + plane_config->fb->base.width = ((val >> 16) & 0xfff) + 1;
> + plane_config->fb->base.height = ((val >> 0) & 0xfff) + 1;
> +
> + val = I915_READ(DSPSTRIDE(pipe));
> + plane_config->fb->base.pitches[0] = val & 0xffffff80;
> +
> + plane_config->size = ALIGN(plane_config->fb->base.pitches[0] *
> + plane_config->fb->base.height, PAGE_SIZE);
This underestimates the size of a tiled framebuffer. Height should be
aligned to 1,16,64 depending on tiling.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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