On Thu, 2013-12-05 at 15:51 +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> The new HSW watermark code can now handle ILK/SNB/IVB as well, so
> switch them over. Kill the old code.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 656 +----------------------------------
> 2 files changed, 12 insertions(+), 646 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3c59b67..24066cc 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11208,7 +11208,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
> pll->on = false;
> }
>
> - if (IS_HASWELL(dev))
> + if (HAS_PCH_SPLIT(dev))
> ilk_wm_get_hw_state(dev);
>
> if (force_restore) {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 420be2f..8b97893 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -965,65 +965,6 @@ static const struct intel_watermark_params i830_wm_info = {
> I830_FIFO_LINE_SIZE
> };
>
> -static const struct intel_watermark_params ironlake_display_wm_info = {
> - ILK_DISPLAY_FIFO,
> - ILK_DISPLAY_MAXWM,
> - ILK_DISPLAY_DFTWM,
> - 2,
> - ILK_FIFO_LINE_SIZE
> -};
> -static const struct intel_watermark_params ironlake_cursor_wm_info = {
> - ILK_CURSOR_FIFO,
> - ILK_CURSOR_MAXWM,
> - ILK_CURSOR_DFTWM,
> - 2,
> - ILK_FIFO_LINE_SIZE
> -};
> -static const struct intel_watermark_params ironlake_display_srwm_info = {
> - ILK_DISPLAY_SR_FIFO,
> - ILK_DISPLAY_MAX_SRWM,
> - ILK_DISPLAY_DFT_SRWM,
> - 2,
> - ILK_FIFO_LINE_SIZE
> -};
> -static const struct intel_watermark_params ironlake_cursor_srwm_info = {
> - ILK_CURSOR_SR_FIFO,
> - ILK_CURSOR_MAX_SRWM,
> - ILK_CURSOR_DFT_SRWM,
> - 2,
> - ILK_FIFO_LINE_SIZE
> -};
> -
> -static const struct intel_watermark_params sandybridge_display_wm_info = {
> - SNB_DISPLAY_FIFO,
> - SNB_DISPLAY_MAXWM,
> - SNB_DISPLAY_DFTWM,
> - 2,
> - SNB_FIFO_LINE_SIZE
> -};
> -static const struct intel_watermark_params sandybridge_cursor_wm_info = {
> - SNB_CURSOR_FIFO,
> - SNB_CURSOR_MAXWM,
> - SNB_CURSOR_DFTWM,
> - 2,
> - SNB_FIFO_LINE_SIZE
> -};
> -static const struct intel_watermark_params sandybridge_display_srwm_info = {
> - SNB_DISPLAY_SR_FIFO,
> - SNB_DISPLAY_MAX_SRWM,
> - SNB_DISPLAY_DFT_SRWM,
> - 2,
> - SNB_FIFO_LINE_SIZE
> -};
> -static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
> - SNB_CURSOR_SR_FIFO,
> - SNB_CURSOR_MAX_SRWM,
> - SNB_CURSOR_DFT_SRWM,
> - 2,
> - SNB_FIFO_LINE_SIZE
> -};
We could also remove now the above macros.
> -
> -
> /**
> * intel_calculate_wm - calculate watermark level
> * @clock_in_khz: pixel clock
> @@ -1707,423 +1648,6 @@ static void i830_update_wm(struct drm_crtc *unused_crtc)
> I915_WRITE(FW_BLC, fwater_lo);
> }
>
> -/*
> - * Check the wm result.
> - *
> - * If any calculated watermark values is larger than the maximum value that
> - * can be programmed into the associated watermark register, that watermark
> - * must be disabled.
> - */
> -static bool ironlake_check_srwm(struct drm_device *dev, int level,
> - int fbc_wm, int display_wm, int cursor_wm,
> - const struct intel_watermark_params *display,
> - const struct intel_watermark_params *cursor)
> -{
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> - DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
> - " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
> -
> - if (fbc_wm > SNB_FBC_MAX_SRWM) {
> - DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
> - fbc_wm, SNB_FBC_MAX_SRWM, level);
> -
> - /* fbc has it's own way to disable FBC WM */
> - I915_WRITE(DISP_ARB_CTL,
> - I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
> - return false;
> - } else if (INTEL_INFO(dev)->gen >= 6) {
> - /* enable FBC WM (except on ILK, where it must remain off) */
> - I915_WRITE(DISP_ARB_CTL,
> - I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
> - }
> -
> - if (display_wm > display->max_wm) {
> - DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
> - display_wm, SNB_DISPLAY_MAX_SRWM, level);
> - return false;
> - }
> -
> - if (cursor_wm > cursor->max_wm) {
> - DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
> - cursor_wm, SNB_CURSOR_MAX_SRWM, level);
> - return false;
> - }
> -
> - if (!(fbc_wm || display_wm || cursor_wm)) {
> - DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
> - return false;
> - }
> -
> - return true;
> -}
> -
> -/*
> - * Compute watermark values of WM[1-3],
> - */
> -static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
> - int latency_ns,
> - const struct intel_watermark_params *display,
> - const struct intel_watermark_params *cursor,
> - int *fbc_wm, int *display_wm, int *cursor_wm)
> -{
> - struct drm_crtc *crtc;
> - const struct drm_display_mode *adjusted_mode;
> - unsigned long line_time_us;
> - int hdisplay, htotal, pixel_size, clock;
> - int line_count, line_size;
> - int small, large;
> - int entries;
> -
> - if (!latency_ns) {
> - *fbc_wm = *display_wm = *cursor_wm = 0;
> - return false;
> - }
> -
> - crtc = intel_get_crtc_for_plane(dev, plane);
> - adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
> - clock = adjusted_mode->crtc_clock;
> - htotal = adjusted_mode->crtc_htotal;
> - hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
> - pixel_size = crtc->fb->bits_per_pixel / 8;
> -
> - line_time_us = (htotal * 1000) / clock;
> - line_count = (latency_ns / line_time_us + 1000) / 1000;
> - line_size = hdisplay * pixel_size;
> -
> - /* Use the minimum of the small and large buffer method for primary */
> - small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
> - large = line_count * line_size;
> -
> - entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
> - *display_wm = entries + display->guard_size;
> -
> - /*
> - * Spec says:
> - * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
> - */
> - *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
> -
> - /* calculate the self-refresh watermark for display cursor */
> - entries = line_count * pixel_size * 64;
> - entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
> - *cursor_wm = entries + cursor->guard_size;
> -
> - return ironlake_check_srwm(dev, level,
> - *fbc_wm, *display_wm, *cursor_wm,
> - display, cursor);
> -}
> -
> -static void ironlake_update_wm(struct drm_crtc *crtc)
> -{
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - int fbc_wm, plane_wm, cursor_wm;
> - unsigned int enabled;
> -
> - enabled = 0;
> - if (g4x_compute_wm0(dev, PIPE_A,
> - &ironlake_display_wm_info,
> - dev_priv->wm.pri_latency[0] * 100,
> - &ironlake_cursor_wm_info,
> - dev_priv->wm.cur_latency[0] * 100,
> - &plane_wm, &cursor_wm)) {
> - I915_WRITE(WM0_PIPEA_ILK,
> - (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
> - DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
> - " plane %d, " "cursor: %d\n",
> - plane_wm, cursor_wm);
> - enabled |= 1 << PIPE_A;
> - }
> -
> - if (g4x_compute_wm0(dev, PIPE_B,
> - &ironlake_display_wm_info,
> - dev_priv->wm.pri_latency[0] * 100,
> - &ironlake_cursor_wm_info,
> - dev_priv->wm.cur_latency[0] * 100,
> - &plane_wm, &cursor_wm)) {
> - I915_WRITE(WM0_PIPEB_ILK,
> - (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
> - DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
> - " plane %d, cursor: %d\n",
> - plane_wm, cursor_wm);
> - enabled |= 1 << PIPE_B;
> - }
> -
> - /*
> - * Calculate and update the self-refresh watermark only when one
> - * display plane is used.
> - */
> - I915_WRITE(WM3_LP_ILK, 0);
> - I915_WRITE(WM2_LP_ILK, 0);
> - I915_WRITE(WM1_LP_ILK, 0);
> -
> - if (!single_plane_enabled(enabled))
> - return;
> - enabled = ffs(enabled) - 1;
> -
> - /* WM1 */
> - if (!ironlake_compute_srwm(dev, 1, enabled,
> - dev_priv->wm.pri_latency[1] * 500,
> - &ironlake_display_srwm_info,
> - &ironlake_cursor_srwm_info,
> - &fbc_wm, &plane_wm, &cursor_wm))
> - return;
> -
> - I915_WRITE(WM1_LP_ILK,
> - WM1_LP_SR_EN |
> - (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
> - (fbc_wm << WM1_LP_FBC_SHIFT) |
> - (plane_wm << WM1_LP_SR_SHIFT) |
> - cursor_wm);
> -
> - /* WM2 */
> - if (!ironlake_compute_srwm(dev, 2, enabled,
> - dev_priv->wm.pri_latency[2] * 500,
> - &ironlake_display_srwm_info,
> - &ironlake_cursor_srwm_info,
> - &fbc_wm, &plane_wm, &cursor_wm))
> - return;
> -
> - I915_WRITE(WM2_LP_ILK,
> - WM2_LP_EN |
> - (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
> - (fbc_wm << WM1_LP_FBC_SHIFT) |
> - (plane_wm << WM1_LP_SR_SHIFT) |
> - cursor_wm);
> -
> - /*
> - * WM3 is unsupported on ILK, probably because we don't have latency
> - * data for that power state
> - */
> -}
> -
> -static void sandybridge_update_wm(struct drm_crtc *crtc)
> -{
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
> - u32 val;
> - int fbc_wm, plane_wm, cursor_wm;
> - unsigned int enabled;
> -
> - enabled = 0;
> - if (g4x_compute_wm0(dev, PIPE_A,
> - &sandybridge_display_wm_info, latency,
> - &sandybridge_cursor_wm_info, latency,
> - &plane_wm, &cursor_wm)) {
> - val = I915_READ(WM0_PIPEA_ILK);
> - val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
> - I915_WRITE(WM0_PIPEA_ILK, val |
> - ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
> - DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
> - " plane %d, " "cursor: %d\n",
> - plane_wm, cursor_wm);
> - enabled |= 1 << PIPE_A;
> - }
> -
> - if (g4x_compute_wm0(dev, PIPE_B,
> - &sandybridge_display_wm_info, latency,
> - &sandybridge_cursor_wm_info, latency,
> - &plane_wm, &cursor_wm)) {
> - val = I915_READ(WM0_PIPEB_ILK);
> - val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
> - I915_WRITE(WM0_PIPEB_ILK, val |
> - ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
> - DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
> - " plane %d, cursor: %d\n",
> - plane_wm, cursor_wm);
> - enabled |= 1 << PIPE_B;
> - }
> -
> - /*
> - * Calculate and update the self-refresh watermark only when one
> - * display plane is used.
> - *
> - * SNB support 3 levels of watermark.
> - *
> - * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
> - * and disabled in the descending order
> - *
> - */
> - I915_WRITE(WM3_LP_ILK, 0);
> - I915_WRITE(WM2_LP_ILK, 0);
> - I915_WRITE(WM1_LP_ILK, 0);
> -
> - if (!single_plane_enabled(enabled) ||
> - dev_priv->sprite_scaling_enabled)
> - return;
> - enabled = ffs(enabled) - 1;
> -
> - /* WM1 */
> - if (!ironlake_compute_srwm(dev, 1, enabled,
> - dev_priv->wm.pri_latency[1] * 500,
> - &sandybridge_display_srwm_info,
> - &sandybridge_cursor_srwm_info,
> - &fbc_wm, &plane_wm, &cursor_wm))
> - return;
> -
> - I915_WRITE(WM1_LP_ILK,
> - WM1_LP_SR_EN |
> - (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
> - (fbc_wm << WM1_LP_FBC_SHIFT) |
> - (plane_wm << WM1_LP_SR_SHIFT) |
> - cursor_wm);
> -
> - /* WM2 */
> - if (!ironlake_compute_srwm(dev, 2, enabled,
> - dev_priv->wm.pri_latency[2] * 500,
> - &sandybridge_display_srwm_info,
> - &sandybridge_cursor_srwm_info,
> - &fbc_wm, &plane_wm, &cursor_wm))
> - return;
> -
> - I915_WRITE(WM2_LP_ILK,
> - WM2_LP_EN |
> - (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
> - (fbc_wm << WM1_LP_FBC_SHIFT) |
> - (plane_wm << WM1_LP_SR_SHIFT) |
> - cursor_wm);
> -
> - /* WM3 */
> - if (!ironlake_compute_srwm(dev, 3, enabled,
> - dev_priv->wm.pri_latency[3] * 500,
> - &sandybridge_display_srwm_info,
> - &sandybridge_cursor_srwm_info,
> - &fbc_wm, &plane_wm, &cursor_wm))
> - return;
> -
> - I915_WRITE(WM3_LP_ILK,
> - WM3_LP_EN |
> - (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
> - (fbc_wm << WM1_LP_FBC_SHIFT) |
> - (plane_wm << WM1_LP_SR_SHIFT) |
> - cursor_wm);
> -}
> -
> -static void ivybridge_update_wm(struct drm_crtc *crtc)
> -{
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
> - u32 val;
> - int fbc_wm, plane_wm, cursor_wm;
> - int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
> - unsigned int enabled;
> -
> - enabled = 0;
> - if (g4x_compute_wm0(dev, PIPE_A,
> - &sandybridge_display_wm_info, latency,
> - &sandybridge_cursor_wm_info, latency,
> - &plane_wm, &cursor_wm)) {
> - val = I915_READ(WM0_PIPEA_ILK);
> - val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
> - I915_WRITE(WM0_PIPEA_ILK, val |
> - ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
> - DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
> - " plane %d, " "cursor: %d\n",
> - plane_wm, cursor_wm);
> - enabled |= 1 << PIPE_A;
> - }
> -
> - if (g4x_compute_wm0(dev, PIPE_B,
> - &sandybridge_display_wm_info, latency,
> - &sandybridge_cursor_wm_info, latency,
> - &plane_wm, &cursor_wm)) {
> - val = I915_READ(WM0_PIPEB_ILK);
> - val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
> - I915_WRITE(WM0_PIPEB_ILK, val |
> - ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
> - DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
> - " plane %d, cursor: %d\n",
> - plane_wm, cursor_wm);
> - enabled |= 1 << PIPE_B;
> - }
> -
> - if (g4x_compute_wm0(dev, PIPE_C,
> - &sandybridge_display_wm_info, latency,
> - &sandybridge_cursor_wm_info, latency,
> - &plane_wm, &cursor_wm)) {
> - val = I915_READ(WM0_PIPEC_IVB);
> - val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
> - I915_WRITE(WM0_PIPEC_IVB, val |
> - ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
> - DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
> - " plane %d, cursor: %d\n",
> - plane_wm, cursor_wm);
> - enabled |= 1 << PIPE_C;
> - }
> -
> - /*
> - * Calculate and update the self-refresh watermark only when one
> - * display plane is used.
> - *
> - * SNB support 3 levels of watermark.
> - *
> - * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
> - * and disabled in the descending order
> - *
> - */
> - I915_WRITE(WM3_LP_ILK, 0);
> - I915_WRITE(WM2_LP_ILK, 0);
> - I915_WRITE(WM1_LP_ILK, 0);
> -
> - if (!single_plane_enabled(enabled) ||
> - dev_priv->sprite_scaling_enabled)
> - return;
> - enabled = ffs(enabled) - 1;
> -
> - /* WM1 */
> - if (!ironlake_compute_srwm(dev, 1, enabled,
> - dev_priv->wm.pri_latency[1] * 500,
> - &sandybridge_display_srwm_info,
> - &sandybridge_cursor_srwm_info,
> - &fbc_wm, &plane_wm, &cursor_wm))
> - return;
> -
> - I915_WRITE(WM1_LP_ILK,
> - WM1_LP_SR_EN |
> - (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
> - (fbc_wm << WM1_LP_FBC_SHIFT) |
> - (plane_wm << WM1_LP_SR_SHIFT) |
> - cursor_wm);
> -
> - /* WM2 */
> - if (!ironlake_compute_srwm(dev, 2, enabled,
> - dev_priv->wm.pri_latency[2] * 500,
> - &sandybridge_display_srwm_info,
> - &sandybridge_cursor_srwm_info,
> - &fbc_wm, &plane_wm, &cursor_wm))
> - return;
> -
> - I915_WRITE(WM2_LP_ILK,
> - WM2_LP_EN |
> - (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
> - (fbc_wm << WM1_LP_FBC_SHIFT) |
> - (plane_wm << WM1_LP_SR_SHIFT) |
> - cursor_wm);
> -
> - /* WM3, note we have to correct the cursor latency */
> - if (!ironlake_compute_srwm(dev, 3, enabled,
> - dev_priv->wm.pri_latency[3] * 500,
> - &sandybridge_display_srwm_info,
> - &sandybridge_cursor_srwm_info,
> - &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
> - !ironlake_compute_srwm(dev, 3, enabled,
> - dev_priv->wm.cur_latency[3] * 500,
> - &sandybridge_display_srwm_info,
> - &sandybridge_cursor_srwm_info,
> - &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
> - return;
> -
> - I915_WRITE(WM3_LP_ILK,
> - WM3_LP_EN |
> - (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
> - (fbc_wm << WM1_LP_FBC_SHIFT) |
> - (plane_wm << WM1_LP_SR_SHIFT) |
> - cursor_wm);
> -}
> -
> static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
> struct drm_crtc *crtc)
> {
> @@ -3059,168 +2583,6 @@ static void haswell_update_sprite_wm(struct drm_plane *plane,
> haswell_update_wm(crtc);
> }
>
> -static bool
> -sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
> - uint32_t sprite_width, int pixel_size,
> - const struct intel_watermark_params *display,
> - int display_latency_ns, int *sprite_wm)
> -{
> - struct drm_crtc *crtc;
> - int clock;
> - int entries, tlb_miss;
> -
> - crtc = intel_get_crtc_for_plane(dev, plane);
> - if (!intel_crtc_active(crtc)) {
> - *sprite_wm = display->guard_size;
> - return false;
> - }
> -
> - clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
> -
> - /* Use the small buffer method to calculate the sprite watermark */
> - entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
> - tlb_miss = display->fifo_size*display->cacheline_size -
> - sprite_width * 8;
> - if (tlb_miss > 0)
> - entries += tlb_miss;
> - entries = DIV_ROUND_UP(entries, display->cacheline_size);
> - *sprite_wm = entries + display->guard_size;
> - if (*sprite_wm > (int)display->max_wm)
> - *sprite_wm = display->max_wm;
> -
> - return true;
> -}
> -
> -static bool
> -sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
> - uint32_t sprite_width, int pixel_size,
> - const struct intel_watermark_params *display,
> - int latency_ns, int *sprite_wm)
> -{
> - struct drm_crtc *crtc;
> - unsigned long line_time_us;
> - int clock;
> - int line_count, line_size;
> - int small, large;
> - int entries;
> -
> - if (!latency_ns) {
> - *sprite_wm = 0;
> - return false;
> - }
> -
> - crtc = intel_get_crtc_for_plane(dev, plane);
> - clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
> - if (!clock) {
> - *sprite_wm = 0;
> - return false;
> - }
> -
> - line_time_us = (sprite_width * 1000) / clock;
> - if (!line_time_us) {
> - *sprite_wm = 0;
> - return false;
> - }
> -
> - line_count = (latency_ns / line_time_us + 1000) / 1000;
> - line_size = sprite_width * pixel_size;
> -
> - /* Use the minimum of the small and large buffer method for primary */
> - small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
> - large = line_count * line_size;
> -
> - entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
> - *sprite_wm = entries + display->guard_size;
> -
> - return *sprite_wm > 0x3ff ? false : true;
> -}
> -
> -static void sandybridge_update_sprite_wm(struct drm_plane *plane,
> - struct drm_crtc *crtc,
> - uint32_t sprite_width, int pixel_size,
> - bool enabled, bool scaled)
> -{
> - struct drm_device *dev = plane->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - int pipe = to_intel_plane(plane)->pipe;
> - int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
> - u32 val;
> - int sprite_wm, reg;
> - int ret;
> -
> - if (!enabled)
> - return;
> -
> - switch (pipe) {
> - case 0:
> - reg = WM0_PIPEA_ILK;
> - break;
> - case 1:
> - reg = WM0_PIPEB_ILK;
> - break;
> - case 2:
> - reg = WM0_PIPEC_IVB;
> - break;
> - default:
> - return; /* bad pipe */
> - }
> -
> - ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
> - &sandybridge_display_wm_info,
> - latency, &sprite_wm);
> - if (!ret) {
> - DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
> - pipe_name(pipe));
> - return;
> - }
> -
> - val = I915_READ(reg);
> - val &= ~WM0_PIPE_SPRITE_MASK;
> - I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
> - DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
> -
> -
> - ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
> - pixel_size,
> - &sandybridge_display_srwm_info,
> - dev_priv->wm.spr_latency[1] * 500,
> - &sprite_wm);
> - if (!ret) {
> - DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
> - pipe_name(pipe));
> - return;
> - }
> - I915_WRITE(WM1S_LP_ILK, sprite_wm);
> -
> - /* Only IVB has two more LP watermarks for sprite */
> - if (!IS_IVYBRIDGE(dev))
> - return;
> -
> - ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
> - pixel_size,
> - &sandybridge_display_srwm_info,
> - dev_priv->wm.spr_latency[2] * 500,
> - &sprite_wm);
> - if (!ret) {
> - DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
> - pipe_name(pipe));
> - return;
> - }
> - I915_WRITE(WM2S_LP_IVB, sprite_wm);
> -
> - ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
> - pixel_size,
> - &sandybridge_display_srwm_info,
> - dev_priv->wm.spr_latency[3] * 500,
> - &sprite_wm);
> - if (!ret) {
> - DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
> - pipe_name(pipe));
> - return;
> - }
> - I915_WRITE(WM3S_LP_IVB, sprite_wm);
> -}
> -
> static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
> {
> struct drm_device *dev = crtc->dev;
> @@ -6072,9 +5434,11 @@ void intel_init_pm(struct drm_device *dev)
> if (IS_GEN5(dev)) {
> if (dev_priv->wm.pri_latency[1] &&
> dev_priv->wm.spr_latency[1] &&
> - dev_priv->wm.cur_latency[1])
> - dev_priv->display.update_wm = ironlake_update_wm;
> - else {
> + dev_priv->wm.cur_latency[1]) {
> + dev_priv->display.update_wm = haswell_update_wm;
> + dev_priv->display.update_sprite_wm =
> + haswell_update_sprite_wm;
ironlake would be a better prefix now.
--Imre
> + } else {
> DRM_DEBUG_KMS("Failed to get proper latency. "
> "Disable CxSR\n");
> dev_priv->display.update_wm = NULL;
> @@ -6084,8 +5448,9 @@ void intel_init_pm(struct drm_device *dev)
> if (dev_priv->wm.pri_latency[0] &&
> dev_priv->wm.spr_latency[0] &&
> dev_priv->wm.cur_latency[0]) {
> - dev_priv->display.update_wm = sandybridge_update_wm;
> - dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
> + dev_priv->display.update_wm = haswell_update_wm;
> + dev_priv->display.update_sprite_wm =
> + haswell_update_sprite_wm;
> } else {
> DRM_DEBUG_KMS("Failed to read display plane latency. "
> "Disable CxSR\n");
> @@ -6096,8 +5461,9 @@ void intel_init_pm(struct drm_device *dev)
> if (dev_priv->wm.pri_latency[0] &&
> dev_priv->wm.spr_latency[0] &&
> dev_priv->wm.cur_latency[0]) {
> - dev_priv->display.update_wm = ivybridge_update_wm;
> - dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
> + dev_priv->display.update_wm = haswell_update_wm;
> + dev_priv->display.update_sprite_wm =
> + haswell_update_sprite_wm;
> } else {
> DRM_DEBUG_KMS("Failed to read display plane latency. "
> "Disable CxSR\n");
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