On Wed, Dec 04, 2013 at 09:09:22PM +0100, Bruno Prémont wrote:
> [ 1.621199] [drm:intel_pipe_config_compare] *ERROR* mismatch in adjusted_mode.crtc_clock (expected 108000, found 48000)
Hmm. Kind of looks like we're reading/parsing the PLL registers incorrectly.
Let's try to see what the driver thinks the registers contain:
>From 4a804c01e051b2cb853d3d5114ae77d1646fb889 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@xxxxxxxxxxxxxxx>
Date: Thu, 5 Dec 2013 12:44:27 +0200
Subject: [PATCH] dpll state debug
---
drivers/gpu/drm/i915/intel_display.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3f2f1d2..b8f9077 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8976,6 +8976,10 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
+ DRM_DEBUG_KMS("DPLL = 0x%x\n", pipe_config->dpll_hw_state.dpll);
+ DRM_DEBUG_KMS("DPLL_MD = 0x%x\n", pipe_config->dpll_hw_state.dpll_md);
+ DRM_DEBUG_KMS("FP0 = 0x%x\n", pipe_config->dpll_hw_state.fp0);
+ DRM_DEBUG_KMS("FP1 = 0x%x\n", pipe_config->dpll_hw_state.fp1);
}
static bool check_encoder_cloning(struct drm_crtc *crtc)
--
1.8.3.2
--
Ville Syrjälä
Intel OTC
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