On Tue, Mar 18, 2025 at 01:05:39PM +0530, Ankit Nautiyal wrote: > Currently, the VRR timing generator is used only when VRR is enabled by > userspace for sinks that support VRR. Starting with PTL+, gradually move > away from the legacy timing generator and use the VRR timing generator > for both variable and fixed timings. > > Note: For platforms where we always enable the VRR timing generator, > the LRR fastset is not allowed to avoid live programming of vrr.guardband > with VRR TG enabled. This effectively breaks the LRR fastset functionality > for these platforms and needs to be addressed. > > v2: Use this for PTL for now to avoid losing LRR fastset for older > platforms. (Ville) > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_vrr.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index c1cdd1918c19..6c6bb868381c 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -553,7 +553,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display) > if (!HAS_VRR(display)) > return false; > > - /* #TODO return true for platforms supporting fixed_rr */ > + if (DISPLAY_VER(display) >= 30) > + return true; > + > return false; > } > > -- > 2.45.2 -- Ville Syrjälä Intel
