This patchset is implementing workaround for underrun on idle PSR HW bug. It is adding notification mechanisms toward PSR for pipe enable/disable, vblank enable/disable and enabling disabling DC5/DC6. These notifications are used to apply/remove the workaround. Current mechanism to block DC states while vblank is enabled on Panel Replay capable system is extended to work for this new workaround as well. Jouni Högander (11): drm/i915/psr: Store enabled non-psr pipes into intel_crtc_state drm/i915/dmc: Add PIPEDMC_EVT_CTL register definition drm/i915/dmc: Add PIPEDMC_BLOCK_PKGC_SW definitions drm/i915/psr: Write PIPEDMC_BLOCK_PKGC_SW when enabling PSR drm/i915/psr: Add mechanism to notify PSR of pipe enable/disable drm/i915/psr: Add mechanism to notify PSR of DC5/6 enable disable drm/i915/psr: Add interface to notify PSR of vblank enable/disable drm/i915/psr: Apply underrun on PSR idle workaround drm/i915/display: Rename intel_psr_needs_block_dc_vblank drm/i915/display: Rename vblank DC workaround functions and variables drm/i915/psr: Check transcoder Selective Update support for PR as well drivers/gpu/drm/i915/display/intel_crtc.c | 6 +- drivers/gpu/drm/i915/display/intel_display.c | 4 + .../gpu/drm/i915/display/intel_display_core.h | 6 +- .../drm/i915/display/intel_display_driver.c | 3 + .../gpu/drm/i915/display/intel_display_irq.c | 27 +- .../i915/display/intel_display_power_well.c | 4 + .../drm/i915/display/intel_display_types.h | 5 +- drivers/gpu/drm/i915/display/intel_dmc_regs.h | 14 + drivers/gpu/drm/i915/display/intel_psr.c | 287 +++++++++++++++++- drivers/gpu/drm/i915/display/intel_psr.h | 8 +- 10 files changed, 327 insertions(+), 37 deletions(-) -- 2.43.0
