On Wed, Mar 05, 2025 at 05:00:26PM +0000, Sebastian Brzezinka wrote: > Hi Ville > > On Wed Mar 5, 2025 at 3:26 PM UTC, Ville Syrjälä wrote: > > On Wed, Mar 05, 2025 at 02:49:46PM +0000, Sebastian Brzezinka wrote: > >> This reverts commit 0ddae025ab6cefa9aba757da3cd1d27908d70b0e. > >> > >> According to bspec 14181, CACHE_MODE_0 is a register that's under userspace > >> control, and DISABLE_REPACKING_FOR_COMPRESSION workaround should be already > >> in all recent Mesa releases. So, there is no need to include it in kernel. > > > > igt doesn't have it. > > > >> > >> Also, this workaround·sporadically fails to load: > >> ``` > >> ERROR GT0: engine workaround lost on application! (reg[7000]=0x0, > >> relevant bits were 0x0 vs expected 0x8000) > >> ``` > > > > If it somehow fails to load from the kernel why would it > > work from userspace? > > > > Hmm, apparently CACHE_MODE_0 needs the mcr steering stuff. > > Does that fix the verification fail? > > Thanks for sugestion. Right now I think that I try to move this wa to > icl_ctx_workarounds_init as both Mat and Chriss notice that register > is a part of the context. Hmm, didn't realize there was a separate list for that. It looks to me like there are a bunch of context saved registers handled in the enging_ctx() stuff currently. I think someone needs to go through all this stuff and relocate all the registers to their correct spots. -- Ville Syrjälä Intel
