On Mon, 24 Feb 2025, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Add the bit definitions needed for POST_LT_ADJ sequence. > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > include/drm/display/drm_dp.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h > index c413ef68f9a3..260948a8f550 100644 > --- a/include/drm/display/drm_dp.h > +++ b/include/drm/display/drm_dp.h > @@ -115,6 +115,7 @@ > > #define DP_MAX_LANE_COUNT 0x002 > # define DP_MAX_LANE_COUNT_MASK 0x1f > +# define DP_POST_LT_ADJ_REQ_SUPPORTED (1 << 5) /* 1.3 */ > # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ > # define DP_ENHANCED_FRAME_CAP (1 << 7) > > @@ -571,6 +572,7 @@ > > #define DP_LANE_COUNT_SET 0x101 > # define DP_LANE_COUNT_MASK 0x0f > +# define DP_POST_LT_ADJ_REQ_GRANTED (1 << 5) /* 1.3 */ > # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) > > #define DP_TRAINING_PATTERN_SET 0x102 > @@ -791,6 +793,7 @@ > #define DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE (1 << 2) /* 2.0 E11 */ > #define DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE (1 << 3) /* 2.0 E11 */ > #define DP_128B132B_LT_FAILED (1 << 4) /* 2.0 E11 */ > +#define DP_POST_LT_ADJ_REQ_IN_PROGRESS (1 << 5) /* 1.3 */ Should be bit 1. Bit 5 is reserved. BR, Jani. > #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) > #define DP_LINK_STATUS_UPDATED (1 << 7) -- Jani Nikula, Intel
