> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, February 19, 2025 2:29 AM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: intel-xe@xxxxxxxxxxxxxxxxxxxxx
> Subject: [PATCH 3/4] drm/i915/dsb: Allow DSB based commits when scalers are in
> use
>
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Have DSB perform plane scaler programming as well. Changes to pfit/pipe scaler
> are not being done on the dsb since those take the fastset path. However we do
> now allow DSB based plane updates when the pfit/pipe scaler is currently
> enabled (the pfit/pipe scaler just won't be touched by the DSB).
>
> Fortunately the hardware issue where some scaler registers are latched at frame
> start and some at start of vblank has been fixed on icl+ (IIRC), and since DSB is
> tgl+ only we don't have to do any changes to the DSB vblank evasion.
> Not that we handle that hardware issue correctly in the CPU vblank evasion
> either...
Looks good to me.
Reviewed-by: Uma Shankar <uma.shakar@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 826b001a66fa..7fd12abdf969 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7319,8 +7319,6 @@ static void intel_atomic_dsb_prepare(struct
> intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct intel_display *display = to_intel_display(state);
> - const struct intel_crtc_state *old_crtc_state =
> - intel_atomic_get_old_crtc_state(state, crtc);
> struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> @@ -7334,8 +7332,6 @@ static void intel_atomic_dsb_prepare(struct
> intel_atomic_state *state,
> new_crtc_state->use_dsb =
> !new_crtc_state->do_async_flip &&
> (DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) &&
> - !new_crtc_state->scaler_state.scaler_users &&
> - !old_crtc_state->scaler_state.scaler_users &&
> !intel_crtc_needs_modeset(new_crtc_state) &&
> !intel_crtc_needs_fastset(new_crtc_state);
>
> @@ -7345,6 +7341,7 @@ static void intel_atomic_dsb_prepare(struct
> intel_atomic_state *state, static void intel_atomic_dsb_finish(struct
> intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> + struct intel_display *display = to_intel_display(state);
> struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> @@ -7391,6 +7388,10 @@ static void intel_atomic_dsb_finish(struct
> intel_atomic_state *state,
> intel_crtc_planes_update_arm(new_crtc_state->dsb_commit,
> state, crtc);
>
> + if (DISPLAY_VER(display) >= 9)
> + skl_detach_scalers(new_crtc_state->dsb_commit,
> + new_crtc_state);
> +
> if (!new_crtc_state->dsb_color_vblank) {
> intel_dsb_wait_vblanks(new_crtc_state->dsb_commit,
> 1);
>
> --
> 2.45.3
