> -----Original Message----- > From: Intel-xe <intel-xe-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Ville Syrjala > Sent: Wednesday, February 19, 2025 2:29 AM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: intel-xe@xxxxxxxxxxxxxxxxxxxxx > Subject: [PATCH 1/4] drm/i915/dsb: Allow DSB based updates without planes > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > We don't actually need any planes to get updated in order to perform the commit > on the DSB. Allow DSB based updates even when we don't touch planes. The > main benefit here is that pure LUT updates will now go through the DSB path and > therefore we don't have to do vblank evasion/etc. on the CPU. > > I think the reason I had this excluded was that I was originally contemplating using > frame/flip timestamps as a way to complete the commits. But I had to scrap that > idea when it turned out that those timestamp get corrupted when DSB is poking > at random registers. Looks Good to me. Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_display.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 065fdf6dbb88..8d46c092fa4d 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -7332,7 +7332,6 @@ static void intel_atomic_dsb_prepare(struct > intel_atomic_state *state, > > /* FIXME deal with everything */ > new_crtc_state->use_dsb = > - new_crtc_state->update_planes && > !new_crtc_state->do_async_flip && > (DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) && > !new_crtc_state->scaler_state.scaler_users && > -- > 2.45.3
