On Wed, Feb 12, 2025 at 04:45:31PM +0200, Ville Syrjälä wrote: > On Fri, Feb 07, 2025 at 03:35:22PM +0200, Jani Nikula wrote: > > #define _FPA0 0x6040 > > #define _FPA1 0x6044 > > #define _FPB0 0x6048 These at least are only used by the display code, so the script seems to have some issues picking up everything. > ... > > #define _PIPE_MISC2_A 0x7002C > > #define _PIPE_MISC2_B 0x7102C > > #define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B) Those aren't used currently, so that explains why they got left behind. > ... > > #define _PIPEA_FLIPCOUNT_G4X 0x70044 > > #define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X) > ... > > #define _PFA_VSCALE 0x68084 > > #define _PFB_VSCALE 0x68884 > > #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) > ... > > #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) > > #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) And these three seem to be used from gvt only atm. -- Ville Syrjälä Intel
