RE: [PATCH 2/3] drm/i915/reg: Remove some extra blank lines

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> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Jani
> Nikula
> Sent: Friday, February 7, 2025 7:05 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; intel-xe@xxxxxxxxxxxxxxxxxxxxx
> Cc: Nikula, Jani <jani.nikula@xxxxxxxxx>; ville.syrjala@xxxxxxxxxxxxxxx; Deak,
> Imre <imre.deak@xxxxxxxxx>
> Subject: [PATCH 2/3] drm/i915/reg: Remove some extra blank lines
> 
> Remove some blank lines from i915_reg.h primarily to help the scripted
> refactoring coming up, keeping the comments together.
> 
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@xxxxxxxxx>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index da658c3591f0..6e80508b544c
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1016,7 +1016,6 @@
>  /*
>   * Overlay regs
>   */
> -
>  #define OVADD			_MMIO(0x30000)
>  #define DOVSTA			_MMIO(0x30008)
>  #define OC_BUF			(0x3 << 20)
> @@ -1071,7 +1070,6 @@
>  /*
>   * Display engine regs
>   */
> -
>  /* Pipe/transcoder A timing regs */
>  #define _TRANS_HTOTAL_A		0x60000
>  #define _TRANS_HTOTAL_B		0x61000
> @@ -2781,7 +2779,6 @@
>   * functionality covered in PCH_PORT_HOTPLUG is split into
>   * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
>   */
> -
>  #define SHOTPLUG_CTL_DDI				_MMIO(0xc4030)
>  #define   SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin)			(0x8
> << (_HPD_PIN_DDI(hpd_pin) * 4))
>  #define   SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin)		(0x4
> << (_HPD_PIN_DDI(hpd_pin) * 4))
> @@ -2861,7 +2858,6 @@
>  #define  TRANS_DPLL_ENABLE(pipe)	(1 << ((pipe) * 4 + 3))
> 
>  /* transcoder */
> -
>  #define _PCH_TRANS_HTOTAL_A		0xe0000
>  #define _PCH_TRANS_HTOTAL_B		0xe1000
>  #define PCH_TRANS_HTOTAL(pipe)		_MMIO_PIPE(pipe,
> _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
> @@ -3787,7 +3783,6 @@ enum skl_power_gate {
>  /*
>   * SKL Clocks
>   */
> -
>  /* CDCLK_CTL */
>  #define CDCLK_CTL			_MMIO(0x46000)
>  #define  CDCLK_FREQ_SEL_MASK		REG_GENMASK(27, 26)
> --
> 2.39.5





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