On Mon, Jan 27, 2025 at 12:28:45PM +0200, Jouni Högander wrote: > We may have commit which doesn't have any non-arming plane register > writes. In that case there aren't "Frame Change" event before DSB vblank > evasion which hangs as PIPEDSL register is reading as 0 when PSR state is > SRDENT(PSR1) or DEEP_SLEEP(PSR2). Handle this by ensuring "Frame Change" > event at the begin of DSB commit if using PSR/PR. > > v2: use intel_psr_trigger_frame_change_event > > Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 5db2af86d0c8a..67041d76763fe 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -7725,6 +7725,14 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, > intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit, > state, crtc); > > + /* > + * Ensure we have "Frame Change" event when PSR state is > + * SRDENT(PSR1) or DEEP_SLEEP(PSR2). Otherwise DSB vblank > + * evasion hangs as PIPEDSL is reading as 0. > + */ > + intel_psr_trigger_frame_change_event(state, new_crtc_state->dsb_commit, > + crtc); > + > intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit); > > if (intel_crtc_needs_color_update(new_crtc_state)) > -- > 2.43.0 -- Ville Syrjälä Intel
