From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Apparently PTL (or I suppose it could have already happened
in either MTL or LNL, didn't have either one to check) changes
the way the VRR hardwre works by ending the safe window as
soon as the push send is triggered. Reorder our DSB programming
sequence to account for that, and try to make sure we catch any
vblank evasion fails that could cause problems with the new
order.
v2: Fix up the issues with wiating for the vblank delay
so we can make do with a single check of the push bit.
Also do the check for the mmio path.
Avoid legacy cursor updates making a mess of things.
Decode the DSB errors.
Ville Syrjälä (8):
drm/i915/dsb: Move the +1 usec adjustment into dsb_wait_usec()
drm/i915/vrr: Don't send push for legacy cursor updates
drm/i915/vrr: Account for TRANS_PUSH delay
drm/i915/dsb: Compute use_dsb earlier
drm/i915/dsb: Introduce intel_dsb_poll()
drm/i915/vrr: Reorder the DSB "wait for safe window" vs. TRANS_PUSH
drm/i915/vrr: Check that the push send bit is clear after delayed
vblank
drm/i915/dsb: Decode DSB error interrupts
drivers/gpu/drm/i915/display/intel_color.c | 9 +++-
drivers/gpu/drm/i915/display/intel_crtc.c | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 31 +++++++------
drivers/gpu/drm/i915/display/intel_dsb.c | 47 +++++++++++++++++---
drivers/gpu/drm/i915/display/intel_dsb.h | 3 ++
drivers/gpu/drm/i915/display/intel_vrr.c | 31 +++++++++++++
drivers/gpu/drm/i915/display/intel_vrr.h | 2 +
7 files changed, 101 insertions(+), 25 deletions(-)
--
2.45.3
