> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Vinod > Govindapillai > Sent: Friday, January 31, 2025 2:30 AM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; intel-xe@xxxxxxxxxxxxxxxxxxxxx > Cc: Govindapillai, Vinod <vinod.govindapillai@xxxxxxxxx>; Syrjala, Ville > <ville.syrjala@xxxxxxxxx>; Reddy Guddati, Santhosh > <santhosh.reddy.guddati@xxxxxxxxx>; Saarinen, Jani > <jani.saarinen@xxxxxxxxx> > Subject: [PATCH v6 1/7] drm/i915/xe3: add register definitions for fbc dirty > rect support > > Register definitions for FBC dirty rect support > > Bspec: 71675, 73424 Add the reference for 69003 for FBC instances Otherwise LGTM, Reviewed-by: Suraj Kandpal <suraj.kandpal@xxxxxxxxx> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_fbc_regs.h | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h > b/drivers/gpu/drm/i915/display/intel_fbc_regs.h > index ae0699c3c2fe..b1d0161a3196 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h > @@ -100,6 +100,15 @@ > #define FBC_STRIDE_MASK REG_GENMASK(14, 0) > #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, > (x)) > > +#define XE3_FBC_DIRTY_RECT(fbc_id) _MMIO_PIPE((fbc_id), 0x43230, > 0x43270) > +#define FBC_DIRTY_RECT_END_LINE_MASK REG_GENMASK(31, > 16) > +#define FBC_DIRTY_RECT_END_LINE(val) > REG_FIELD_PREP(FBC_DIRTY_RECT_END_LINE_MASK, (val)) > +#define FBC_DIRTY_RECT_START_LINE_MASK REG_GENMASK(15, 0) > +#define FBC_DIRTY_RECT_START_LINE(val) > REG_FIELD_PREP(FBC_DIRTY_RECT_START_LINE_MASK, (val)) > + > +#define XE3_FBC_DIRTY_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x43234, > 0x43274) > +#define FBC_DIRTY_RECT_EN REG_BIT(31) > + > #define ILK_FBC_RT_BASE _MMIO(0x2128) > #define ILK_FBC_RT_VALID REG_BIT(0) > #define SNB_FBC_FRONT_BUFFER REG_BIT(1) > -- > 2.43.0
