VRR timing generator can be used even with fixed refresh rate.
With this the legacy timing generator can be phased out and VRR timing
generator can be used for all cases, whether panels support VRR or not.
Add an enum value to represent the VRR timing generator in
fixed refresh rate mode and update the helper vrrtg_mode_str
for printing it.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx>
---
.../gpu/drm/i915/display/intel_crtc_state_dump.c | 1 +
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 13 ++++++++++---
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 9f4c88f05f4c..08559c6a5095 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -176,6 +176,7 @@ static const char * const vrrtg_mode_str[] = {
[INTEL_VRRTG_MODE_NONE] = "none",
[INTEL_VRRTG_MODE_VRR] = "vrr",
[INTEL_VRRTG_MODE_CMRR] = "cmrr",
+ [INTEL_VRRTG_MODE_FIXED_RR] = "fixed_rr",
};
static const char *intel_vrrtg_mode_name(enum intel_vrrtg_mode mode)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 338cfd99e5d3..edf021db0d31 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -939,6 +939,7 @@ enum intel_vrrtg_mode {
INTEL_VRRTG_MODE_NONE,
INTEL_VRRTG_MODE_VRR,
INTEL_VRRTG_MODE_CMRR,
+ INTEL_VRRTG_MODE_FIXED_RR,
};
struct intel_crtc_state {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 2b4376e985f6..1b522af70696 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -583,15 +583,12 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
TRANS_VRR_CTL(display, cpu_transcoder));
if (HAS_CMRR(display) && trans_vrr_ctl & VRR_CTL_CMRR_ENABLE) {
- crtc_state->vrr.mode = INTEL_VRRTG_MODE_CMRR;
crtc_state->vrr.cmrr_n =
intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
TRANS_CMRR_N_HI(display, cpu_transcoder));
crtc_state->vrr.cmrr_m =
intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
TRANS_CMRR_M_HI(display, cpu_transcoder));
- } else if (trans_vrr_ctl & VRR_CTL_VRR_ENABLE) {
- crtc_state->vrr.mode = INTEL_VRRTG_MODE_VRR;
}
if (DISPLAY_VER(display) >= 13)
@@ -621,6 +618,16 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
}
}
+ if (trans_vrr_ctl & VRR_CTL_VRR_ENABLE) {
+ if (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE)
+ crtc_state->vrr.mode = INTEL_VRRTG_MODE_CMRR;
+ else if (crtc_state->vrr.vmax == crtc_state->vrr.flipline &&
+ crtc_state->vrr.vmin == crtc_state->vrr.flipline)
+ crtc_state->vrr.mode = INTEL_VRRTG_MODE_FIXED_RR;
+ else
+ crtc_state->vrr.mode = INTEL_VRRTG_MODE_VRR;
+ }
+
if (intel_vrr_is_enabled(crtc_state))
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
--
2.45.2
