The VRR timing generator can be used in multiple modes of operation:
dynamic refresh rate (VRR), content-matched refresh rate (CMRR), and
fixed refresh rate (Fixed_RR).
Currently, VRR and CMRR modes are supported, with Fixed_RR mode
forthcoming.
To track the different operational modes of the VRR timing generator,
introduce a new member 'mode' to the VRR struct.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_display_types.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index cb51b7936f93..3195c9f33028 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -935,6 +935,12 @@ void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val);
typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val);
+enum intel_vrrtg_mode {
+ INTEL_VRRTG_MODE_NONE,
+ INTEL_VRRTG_MODE_VRR,
+ INTEL_VRRTG_MODE_CMRR,
+};
+
struct intel_crtc_state {
/*
* uapi (drm) state. This is the software state shown to userspace.
@@ -1306,6 +1312,7 @@ struct intel_crtc_state {
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
u32 vsync_end, vsync_start;
+ enum intel_vrrtg_mode mode;
} vrr;
/* Content Match Refresh Rate state */
--
2.45.2
