Even though the VRR timing generator (TG) is primarily used for
variable refresh rates, it can be used for fixed refresh rates as
well. For a fixed refresh rate the Flip Line and Vmax must be equal
(TRANS_VRR_FLIPLINE = TRANS_VRR_VMAX). Beyond that, there are some
dependencies between the VRR timings and the legacy timing generator
registers.
This series is an attempt to use VRR TG for fixed refresh rate.
For platforms XE2LPD+, always go with VRR timing generator for both fixed and
variable refresh rate cases.
Rev2:
-Added support from MTL+ and for HDMI too.
-Changed VRR VSYNC programming which is required for HDMI.
-Modified vrr compute config for bigjoiner case. (Still to be tested).
Rev3:
-Start support from XE2LPD+ as MTL needs a WA to have PSR +VRR (fixed
refresh rate)
-Add changes to enable PSR with VRR with fixed refresh rate.
Rev4:
-Addressed review comments from Mitul and rebased.
Rev5:
-Avoid MSA Ignore PAR timing enable bit for fixed refresh rate
with VRR TG.
-Skip VRR compute config for HDMI connected via DP-HDMI2.1 PCON.
-Print fixed_rr along with other VRR parameters in crtc state dump.
-Rebase
Rev6:
-Refactor VRR code to have distinct modes in which VRR timing generator
can be used: VRR, FIXED_RR, CMRR.
-Bring the cmmr attributes in vrr struct.
-Remove condition flipline > vmin for LNL.
-Account for vmax being 0 based while MSA vtotal being 1 based.
Rev7:
I have added patches from series for AS SDP fixes [1] , as without panels
that support AS SDP gives a lot of issues.
There were major changes in design as discussed in last version [2].
Below are the change logs:
-Change the design to compute vrr state based on actual uapi.vrr.enable
knob. So when that knob is disabled we always compute vmin=flipline=vmax.
-Always set vmin=crtc_vtotal instead of the using the current refresh rate
based approach. This helps to have the same guardband while switching
between fixed and variable timings.
-Disable CMRR for now to reduce complexity while changing timings on the
fly.
-Change the state computation and add vmin/vmax/flipline reprogramming
to vrr_{enable,disable}()
-Introduce the fixed refresh mode from MTL instead of LNL.
[1] https://patchwork.freedesktop.org/series/137035/
[2] https://patchwork.kernel.org/project/intel-gfx/cover/20241111091221.2992818-1-ankit.k.nautiyal@xxxxxxxxx/
Ankit Nautiyal (30):
drm/i915/dp: fix the Adaptive sync Operation mode for SDP
drm/i915/vrr: Remove unwanted comment
drm/i915:vrr: Refactor VRR timing setup into a separate function
drm/i915:vrr: Separate out functions to compute vmin and vmax
drm/i915/vrr: Make helpers for cmrr and vrr timings
drm/i915/vrr: Avoid prepare vrr timings for cmrr
drm/i915/vrr: Simplify CMRR Enable Check in intel_vrr_get_config
drm/i915/vrr: Introduce new field for VRR mode
drm/i915/vrr: Fill VRR timing generator mode for CMRR and VRR
drm/i915/display: Remove vrr.enable and instead check vrr.mode != NONE
drm/i915/display: Absorb cmrr attributes into vrr struct
drm/i915/display: Add vrr mode to crtc_state dump
drm/i915/dp: Avoid vrr compute config for HDMI sink
drm/i915/vrr: Introduce VRR mode Fixed RR
drm/i915/vrr: Avoid sending PUSH when VRR TG is used with Fixed
refresh rate
drm/i915/display: Enable MSA Ignore Timing PAR only when in not
fixed_rr mode
drm/i915/vrr: Disable CMRR
drm/i915/vrr: Use crtc_vtotal for vmin
drm/i915/vrr: Adjust Vtotal for MSA for fixed timings
drm/i915/vrr: Prepare for fixed refresh rate timings
drm/i915/hdmi: Use VRR Timing generator for HDMI
drm/i915/display: Disable PSR before disabling VRR
drm/i915/psr: Allow PSR for fixed refrsh rate with VRR TG
drm/i915/display: Extend WA 14015406119 for PSR2
drm/i915/vrr: Handle joiner with vrr
drm/i915/vrr: Always set vrr vmax/vmin/flipline in
vrr_{enable/disable}
drm/i915/vrr: Prepare for Fixed refresh rate mode from MTL+
drm/i915/vrr: Refactor condition for computing vmax and LRR
drm/i915/vrr: Always use VRR timing generator for MTL+
drm/i915/display: Use VRR timings for MTL+ in modeset sequence
Mitul Golani (5):
drm/i915/vrr: Add crtc_state dump for vrr.vsync params
drm/i915/vrr: Compute vrr.vsync_{start, end} during full modeset
drm/i915/dp: Compute as_sdp.vtotal based on vrr timings
drm/i915/dp: Compute as_sdp based on if vrr possible
drm/i915/display: Move as sdp params change to fastset
.../drm/i915/display/intel_crtc_state_dump.c | 26 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 79 +++--
.../drm/i915/display/intel_display_types.h | 17 +-
drivers/gpu/drm/i915/display/intel_dp.c | 20 +-
.../drm/i915/display/intel_dp_link_training.c | 8 +-
drivers/gpu/drm/i915/display/intel_dsb.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +
.../drm/i915/display/intel_modeset_setup.c | 3 +-
drivers/gpu/drm/i915/display/intel_psr.c | 7 +-
drivers/gpu/drm/i915/display/intel_vblank.c | 8 +-
drivers/gpu/drm/i915/display/intel_vrr.c | 311 ++++++++++++------
drivers/gpu/drm/i915/display/intel_vrr.h | 7 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 3 +-
14 files changed, 326 insertions(+), 171 deletions(-)
--
2.45.2
