On Fri, Jan 24, 2025 at 11:57:10AM +0000, Hogander, Jouni wrote: > On Fri, 2025-01-24 at 13:39 +0200, Ville Syrjälä wrote: > > On Fri, Jan 24, 2025 at 12:56:22PM +0200, Jouni Högander wrote: > > > PIPEDSL is reading as 0 when in SRDENT(PSR1) or DEEP_SLEEP(PSR2). > > > On > > > wake-up scanline counting starts from vblank_start - 1. We don't > > > know if > > > wake-up is already ongoing when evasion starts. In worst case > > > PIPEDSL could > > > start reading valid value right after checking the scanline. In > > > this > > > scenario we wouldn't have enough time to write all registers. To > > > tackle > > > this evade scanline 0 as well. As a drawback we have 1 frame delay > > > in flip > > > when waking up. > > > > > > Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx> > > > --- > > > drivers/gpu/drm/i915/display/intel_dsb.c | 12 ++++++++++++ > > > 1 file changed, 12 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c > > > b/drivers/gpu/drm/i915/display/intel_dsb.c > > > index bb77ded8bf726..914f0be4491c4 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dsb.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c > > > @@ -528,6 +528,18 @@ void intel_dsb_vblank_evade(struct > > > intel_atomic_state *state, > > > int latency = intel_usecs_to_scanlines(&crtc_state- > > > >hw.adjusted_mode, 20); > > > int start, end; > > > > > > + /* > > > + * PIPEDSL is reading as 0 when in SRDENT(PSR1) or > > > DEEP_SLEEP(PSR2). On > > > + * wake-up scanline counting starts from vblank_start - 1. > > > We don't know > > > + * if wake-up is already ongoing when evasion starts. In > > > worst case > > > + * PIPEDSL could start reading valid value right after > > > checking the > > > + * scanline. In this scenario we wouldn't have enough time > > > to write all > > > + * registers. To tackle this evade scanline 0 as well. As > > > a drawback we > > > + * have 1 frame delay in flip when waking up. > > > + */ > > > + if (crtc_state->has_psr && !crtc_state->has_panel_replay) > > > > What's the deal with panel replay here? > > I couldn't see PIPEDSL returning 0 when using Panel Replay. Even on > same setup with PSR I saw it, but with PR I couldn't see. Hmm. Are you sure it's reaching DC5/6? Though I suppose it's possible that panel replay (unlike PSR) does pretty much everything from the DMC's DC state handler, so as soon as you read the register it restores things fully enough that you get the vblank_start-1 response... -- Ville Syrjälä Intel
