On Thu, 16 Jan 2025, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> intel_set_transcoder_timings() will set TRANS_VBLANK.vblank_start to 0
> for clarity on ADL+ (non-DSI) because the hardware no longer uses that
> value. So the same in intel_set_transcoder_timings_lrr() to make sure
> the registers stay constitent even when doing LRR timing updates.
>
> Cc: Paz Zcharya <pazz@xxxxxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Hmm, so how come this doesn't warrant a change in readout?
Apparently because intel_get_transcoder_timings() overwrites the read
value for display 13+ and non-dsi. Hrmh.
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f5d2eacce119..5ba3b2d658e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2923,6 +2923,14 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
> crtc_vblank_start = adjusted_mode->crtc_vblank_start;
> crtc_vblank_end = adjusted_mode->crtc_vblank_end;
>
> + if (DISPLAY_VER(dev_priv) >= 13) {
> + /*
> + * VBLANK_START not used by hw, just clear it
> + * to make it stand out in register dumps.
> + */
> + crtc_vblank_start = 1;
> + }
> +
> drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
>
> /*
--
Jani Nikula, Intel
