> -----Original Message----- > From: Intel-xe <intel-xe-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Jouni > Högander > Sent: Thursday, January 9, 2025 1:02 PM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; intel-xe@xxxxxxxxxxxxxxxxxxxxx > Cc: Hogander, Jouni <jouni.hogander@xxxxxxxxx> > Subject: [PATCH v3 04/10] drm/i915/psr: Add register definitions for SFF_CTL > and CFF_CTL registers > > Add register definitions for SFF_CTL and CFF_CTL registers. Name them as > LNL_SFF_CTL and LNL_CFF_CTL. > > v2: use _MMIO_TRANS instead of _MMIO_TRANS2 > > Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx> LNL_CFF_CTL is not used and good to add with its usage. And this can be merged with patch5 but do not have any concern. With this fixed LGTM. Reviewed-by: Animesh Manna <animesh.manna@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > index 9ad7611506e8..795e6b9cc575 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > @@ -251,6 +251,16 @@ > #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME > REG_BIT(14) > #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME > REG_BIT(13) > > +#define _LNL_SFF_CTL_A 0x60918 > +#define _LNL_SFF_CTL_B 0x61918 > +#define LNL_SFF_CTL(tran) _MMIO_TRANS(tran, > _LNL_SFF_CTL_A, _LNL_SFF_CTL_B) > +#define LNL_SFF_CTL_SF_SINGLE_FULL_FRAME REG_BIT(1) > + > +#define _LNL_CFF_CTL_A 0x6091c > +#define _LNL_CFF_CTL_B 0x6191c > +#define LNL_CFF_CTL(tran) _MMIO_TRANS(tran, > _LNL_CFF_CTL_A, _LNL_CFF_CTL_B) > +#define LNL_CFF_CTL_SF_CONTINUOUS_FULL_FRAME REG_BIT(1) > + > /* PSR2 Early transport */ > #define _PIPE_SRCSZ_ERLY_TPT_A 0x70074 > #define _PIPE_SRCSZ_ERLY_TPT_B 0x71074 > -- > 2.43.0
