> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Jouni
> Högander
> Sent: Thursday, January 9, 2025 1:01 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; intel-xe@xxxxxxxxxxxxxxxxxxxxx
> Cc: Hogander, Jouni <jouni.hogander@xxxxxxxxx>
> Subject: [PATCH v3 01/10] drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit
> only to send full update
>
> We are preparing for a change where only frontbuffer flush will use single
> full frame bit of a new register (SFF_CTL) available on LunarLake onwards.
>
> Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 0b021acb330f..476305010e11 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2381,7 +2381,6 @@ static void psr2_man_trk_ctl_calc(struct
> intel_crtc_state *crtc_state,
> val |= man_trk_ctl_partial_frame_bit_get(display);
>
> if (full_update) {
> - val |= man_trk_ctl_single_full_frame_bit_get(display);
Is this change applicable for older platforms before LNL? If no impact good to describe in commit description or code-comment.
Regards,
Animesh
> val |= man_trk_ctl_continuos_full_frame(display);
> goto exit;
> }
> --
> 2.43.0
