Pipe interrupt registers live in their respective pipes' power wells, which are below PG0. That means that they must also be tracked as registers that are powered-off during dynamic DC states. For that, we first convert the display IRQ code to use display-specific MMIO functions so that DMC wakelock checks are properly done and then add the range for pipe interrupts in the table checked by the DMC wakelock code. This series fixes vblank timeouts that were happening due to PIPE interrupt registers being accessed without the DMC wakelock. v2: - Change "drm/i915/display: Wrap IRQ-specific uncore functions" to have the wrappers as static functions inside intel_display_irq.c. Gustavo Sousa (3): drm/i915/display: Use display MMIO functions in intel_display_irq.c drm/i915/display: Wrap IRQ-specific uncore functions drm/i915/dmc_wl: Track pipe interrupt registers .../gpu/drm/i915/display/intel_display_irq.c | 350 ++++++++++-------- drivers/gpu/drm/i915/display/intel_dmc_wl.c | 1 + 2 files changed, 205 insertions(+), 146 deletions(-) -- 2.48.0
