Hi Daniele,
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -5519,12 +5519,20 @@ static inline void guc_log_context(struct drm_printer *p,
> {
> drm_printf(p, "GuC lrc descriptor %u:\n", ce->guc_id.id);
> drm_printf(p, "\tHW Context Desc: 0x%08x\n", ce->lrc.lrca);
> - drm_printf(p, "\t\tLRC Head: Internal %u, Memory %u\n",
> - ce->ring->head,
> - ce->lrc_reg_state[CTX_RING_HEAD]);
> - drm_printf(p, "\t\tLRC Tail: Internal %u, Memory %u\n",
> - ce->ring->tail,
> - ce->lrc_reg_state[CTX_RING_TAIL]);
> + if (intel_context_pin_if_active(ce)) {
> + drm_printf(p, "\t\tLRC Head: Internal %u, Memory %u\n",
> + ce->ring->head,
> + ce->lrc_reg_state[CTX_RING_HEAD]);
> + drm_printf(p, "\t\tLRC Tail: Internal %u, Memory %u\n",
> + ce->ring->tail,
> + ce->lrc_reg_state[CTX_RING_TAIL]);
> + intel_context_unpin(ce);
> + } else {
> + drm_printf(p, "\t\tLRC Head: Internal %u, Memory not pinned\n",
> + ce->ring->head);
> + drm_printf(p, "\t\tLRC Tail: Internal %u, Memory not pinned\n",
> + ce->ring->tail);
> + }
Please note the warnings from checkpatch.pl job. These lines should be
aligned differently.
Krzysztof
>
