On Wed, Jan 08, 2025 at 09:13:14AM -0500, Rodrigo Vivi wrote: > The goal here is to improve the GPU performance in some cases > where we are TDP limited, with both GPU and CPU with high > utilization and PCODE without power to fulfill both sides. > Of course, only matters for integrated parts with GuC > SLPC enabled: ADL and MTL. > > Apparently the ADL on our CI was not happy about that > with the igt_spinners timming out [1]. So, this new attempt > also lift the BAT restriction on the igt_spinner with the > first patch. > > Another possibility would be to make this change for MTL > only, but I'm afraid that this is not the ideal, because: > 1. ADL users couldn't get the performance benefit of this change > 2. This would sound like a hack to bypass CI, where the ADL there > might have some TDP limitation and MTL there having more power. For the records, I have changed my mind here. IBC on ADL was doing balancing even when not TDP limited and perhaps even depending on display metrics. Let's enable it only on MTL+ > > [1] - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_142676v2/bat-twl-2/igt@i915_selftest@live@gt_engines.html > > Thanks, > Rodrigo. > > Rodrigo Vivi (3): > drm/i915: Increase the timeout of the spinners > drm/i915/guc/slpc: Enable GuC SLPC default strategies > drm/i915/guc/slpc: Print more SLPC debug status information > > drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 34 ++++++++++---------- > drivers/gpu/drm/i915/selftests/igt_spinner.c | 2 +- > 2 files changed, 18 insertions(+), 18 deletions(-) > > -- > 2.47.1 >
