User created LUT can be fed back to the hardware so that the hardware
can apply this LUT data to see the enhancement in the image.
Signed-off-by: Arun R Murthy <arun.r.murthy@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_histogram.c | 70 ++++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_histogram.h | 4 ++
2 files changed, 74 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c
index ea61a98efb18fcccce88a8a3b82fd373c47920df..499ea9157a338f5081c74dfc182371b2075634ea 100644
--- a/drivers/gpu/drm/i915/display/intel_histogram.c
+++ b/drivers/gpu/drm/i915/display/intel_histogram.c
@@ -20,6 +20,7 @@
/* Precision factor for threshold guardband */
#define HISTOGRAM_GUARDBAND_PRECISION_FACTOR 10000
#define HISTOGRAM_BIN_READ_RETRY_COUNT 5
+#define IET_SAMPLE_FORMAT_1_INT_9_FRACT 0x1000009
static bool intel_histogram_get_data(struct intel_crtc *intel_crtc)
{
@@ -215,6 +216,60 @@ int intel_histogram_update(struct intel_crtc *intel_crtc,
return 0;
}
+int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc,
+ struct drm_property_blob *blob)
+{
+ struct intel_histogram *histogram = intel_crtc->histogram;
+ struct intel_display *display = to_intel_display(intel_crtc);
+ int pipe = intel_crtc->pipe;
+ int i = 0;
+ struct drm_iet_1dlut_sample *iet;
+ u32 *data;
+ int ret;
+
+ if (!histogram)
+ return -EINVAL;
+
+ if (!histogram->enable) {
+ drm_err(display->drm, "histogram not enabled");
+ return -EINVAL;
+ }
+
+ if (!data) {
+ drm_err(display->drm, "enhancement LUT data is NULL");
+ return -EINVAL;
+ }
+
+ /* Set DPST_CTL Bin Reg function select to IE & wait for a vblabk */
+ intel_de_rmw(display, DPST_CTL(pipe),
+ DPST_CTL_BIN_REG_FUNC_SEL, DPST_CTL_BIN_REG_FUNC_IE);
+
+ drm_crtc_wait_one_vblank(&intel_crtc->base);
+
+ /* Set DPST_CTL Bin Register Index to 0 */
+ intel_de_rmw(display, DPST_CTL(pipe),
+ DPST_CTL_BIN_REG_MASK, DPST_CTL_BIN_REG_CLEAR);
+
+ iet = (struct drm_iet_1dlut_sample *)blob->data;
+ data = kzalloc(sizeof(data) * iet->nr_elements, GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+ ret = copy_from_user(data, (uint32_t __user *)(unsigned long)iet->data_ptr,
+ sizeof(uint32_t) * iet->nr_elements);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) {
+ intel_de_rmw(display, DPST_BIN(pipe),
+ DPST_BIN_DATA_MASK, data[i]);
+ drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", i, data[i]);
+ }
+ kfree(data);
+ drm_property_blob_put(intel_crtc->base.state->iet_lut);
+
+ return 0;
+}
+
void intel_histogram_finish(struct intel_crtc *intel_crtc)
{
struct intel_histogram *histogram = intel_crtc->histogram;
@@ -227,6 +282,8 @@ int intel_histogram_init(struct intel_crtc *crtc)
{
struct intel_histogram *histogram;
struct drm_histogram_caps *histogram_caps;
+ struct drm_iet_caps *iet_caps;
+ u32 *iet_format;
/* Allocate histogram internal struct */
histogram = kzalloc(sizeof(*histogram), GFP_KERNEL);
@@ -239,10 +296,23 @@ int intel_histogram_init(struct intel_crtc *crtc)
histogram_caps->histogram_mode = DRM_MODE_HISTOGRAM_HSV_MAX_RGB;
histogram_caps->bins_count = HISTOGRAM_BIN_COUNT;
+ iet_caps = kzalloc(sizeof(*iet_caps), GFP_KERNEL);
+ if (!iet_caps)
+ return -ENOMEM;
+
+ iet_caps->iet_mode = DRM_MODE_IET_MULTIPLICATIVE;
+ iet_caps->nr_iet_sample_formats = 1;
+ iet_caps->nr_iet_lut_entries = HISTOGRAM_IET_LENGTH;
+ iet_format = kzalloc(sizeof(u32)*iet_caps->nr_iet_sample_formats,
+ GFP_KERNEL);
+ *iet_format = IET_SAMPLE_FORMAT_1_INT_9_FRACT;
+ iet_caps->iet_sample_format = *iet_format;
+
crtc->histogram = histogram;
histogram->crtc = crtc;
histogram->can_enable = false;
histogram->caps = histogram_caps;
+ histogram->iet_caps = iet_caps;
INIT_DEFERRABLE_WORK(&histogram->work,
intel_histogram_handle_int_work);
diff --git a/drivers/gpu/drm/i915/display/intel_histogram.h b/drivers/gpu/drm/i915/display/intel_histogram.h
index b44ba3afc94f79f291f4e5ebdd04dcf9434b48a4..0999d1720c7abee8907c77896e4b1e6ff756160f 100644
--- a/drivers/gpu/drm/i915/display/intel_histogram.h
+++ b/drivers/gpu/drm/i915/display/intel_histogram.h
@@ -18,9 +18,11 @@ struct intel_display;
enum pipe;
#define HISTOGRAM_BIN_COUNT 32
+#define HISTOGRAM_IET_LENGTH 33
struct intel_histogram {
struct drm_histogram_caps *caps;
+ struct drm_iet_caps *iet_caps;
struct intel_crtc *crtc;
struct delayed_work work;
bool enable;
@@ -45,6 +47,8 @@ void intel_histogram_irq_handler(struct intel_display *display, enum pipe pipe);
int intel_histogram_atomic_check(struct intel_crtc *intel_crtc);
int intel_histogram_update(struct intel_crtc *intel_crtc,
struct drm_histogram_config *config);
+int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc,
+ struct drm_property_blob *blob);
int intel_histogram_init(struct intel_crtc *intel_crtc);
void intel_histogram_finish(struct intel_crtc *intel_crtc);
--
2.25.1
