On Fri, 2025-01-03 at 14:41 -0300, Gustavo Sousa wrote:
> Pipe interrupt registers live in their respective pipes' power wells,
> which are below PG0. That means that they must also be tracked as
> registers that are powered-off during dynamic DC states.
>
> There are probably more ranges that we need to track down and add to
> the
> powered_off_ranges. However, let's make this change only about pipe
> interrupt registers to fix some vblank timeouts observed due to the
> DMC
> wakelock not being taken for those registers.
>
> In the future, we might want to replace powered_off_ranges with a new
> table to represent registers in PG0, which should be probably easier
> to
> maintain. Any register not belonging to that table should be
> considered
> powered off during dynamic DC states and, as such, requiring the DMC
> wakelock for access.
>
> Bspec: 72519, 71583
> Signed-off-by: Gustavo Sousa <gustavo.sousa@xxxxxxxxx>
Reviewed-by: Jouni Högander <jouni.hogander@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_dmc_wl.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> index 02de3ae15074..985aa968692e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> @@ -56,6 +56,7 @@ struct intel_dmc_wl_range {
> };
>
> static const struct intel_dmc_wl_range powered_off_ranges[] = {
> + { .start = 0x44400, .end = 0x4447f }, /* PIPE interrupt
> registers */
> { .start = 0x60000, .end = 0x7ffff },
> {},
> };
