> -----Original Message-----
> From: Murthy, Arun R <arun.r.murthy@xxxxxxxxx>
> Sent: Friday, January 3, 2025 10:39 AM
> To: Kandpal, Suraj <suraj.kandpal@xxxxxxxxx>; intel-xe@xxxxxxxxxxxxxxxxxxxxx;
> intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: RE: [PATCHv4] drm/i915/dp: Guarantee a minimum HBlank time
>
> > > -----Original Message-----
> > > From: Intel-xe <intel-xe-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of
> > > Arun R Murthy
> > > Sent: Monday, November 11, 2024 2:56 PM
> > > To: intel-xe@xxxxxxxxxxxxxxxxxxxxx; intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > > Cc: Murthy, Arun R <arun.r.murthy@xxxxxxxxx>
> > > Subject: [PATCHv4] drm/i915/dp: Guarantee a minimum HBlank time
> > >
> > > Mandate a minimum Hblank symbol cycle count between BS and BE in
> > > 8b/10b MST and 12b/132b mode.
> >
> > Missed the typo here *128
> >
> > > Spec: DP2.1a
> > >
> > > v2: Affine calculation/updation of min HBlank to dp_mst (Jani)
> > > v3: moved min_hblank from struct intel_dp to intel_crtc_state (Jani)
> > > v4: use max/min functions, change intel_xx *intel_xx to intel_xx *xx
> > > (Jani)
> > > Limit hblank to 511 and accomodate BS/BE in calculated value
> > > (Srikanth)
> > >
> > > Signed-off-by: Arun R Murthy <arun.r.murthy@xxxxxxxxx>
> > > ---
> > > .../drm/i915/display/intel_crtc_state_dump.c | 1 +
> > > .../drm/i915/display/intel_display_types.h | 1 +
> > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 35
> +++++++++++++++++++
> > > drivers/gpu/drm/i915/i915_reg.h | 4 +++
> > > 4 files changed, 41 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > > b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > > index 705ec5ad385c..f8c1d1dd66a3 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > > @@ -258,6 +258,7 @@ void intel_crtc_state_dump(const struct
> > > intel_crtc_state *pipe_config,
> > > str_enabled_disabled(pipe_config-
> > > >has_sel_update),
> > > str_enabled_disabled(pipe_config-
> > > >has_panel_replay),
> > > str_enabled_disabled(pipe_config-
> > > >enable_psr2_sel_fetch));
> > > + drm_printf(&p, "minimum HBlank: %d\n", pipe_config-
> > > >min_hblank);
> > > }
> >
> > Covers the dump but still missing the checker Also maybe a different
> > patch for this work
> >
> Checker may not be required alike max_link_bpp_x16 since this a must on
> every modeset.
Oh ok.
>
> > >
> > > drm_printf(&p, "framestart delay: %d, MSA timing delay: %d\n",
> > > diff
> > > -- git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index d3a1aa7c919f..d2716addf88e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1075,6 +1075,7 @@ struct intel_crtc_state {
> > >
> > > int max_link_bpp_x16; /* in 1/16 bpp units */
> > > int pipe_bpp; /* in 1 bpp units */
> > > + int min_hblank; /* min HBlank for DP2.1 */
> >
> > Is it only for DP2.1 because we end up filling in both cases if uhbr
> > or not just with different values
> >
> Its for only MST case applicable for both uhbr and non-uhbr rates. The
> minimum calculation values changes based on uhbr/non-uhbr rates.
In that case the comment min HBlank for DP2.1 does not seems right that needs to be changed then
Regards,
Suraj Kandpal
>
> Thanks and Regards,
> Arun R Murthy
> --------------------
