On Thu, Dec 19, 2024 at 11:33:58PM +0200, Jani Nikula wrote:
> It's not very clearly specified, and the hardware bit is ill-named, but
> 128b/132b SST also needs the MST mode set in the DP_TP_CTL register.
>
> This is preparation for enabling 128b/132b SST. This path is not
> reachable yet.
>
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index ce34a619d48a..6f813bf85b23 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3656,7 +3656,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
>
> /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */
> dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
> - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
> + intel_dp_is_uhbr(crtc_state)) {
> dp_tp_ctl |= DP_TP_CTL_MODE_MST;
> } else {
> dp_tp_ctl |= DP_TP_CTL_MODE_SST;
> @@ -3716,7 +3717,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> }
>
> dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
> - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
> + intel_dp_is_uhbr(crtc_state)) {
> dp_tp_ctl |= DP_TP_CTL_MODE_MST;
> } else {
> dp_tp_ctl |= DP_TP_CTL_MODE_SST;
> --
> 2.39.5
>
