> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Gustavo
> Sousa
> Sent: Friday, December 20, 2024 3:44 AM
> To: intel-xe@xxxxxxxxxxxxxxxxxxxxx; intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: [PATCH 3/4] drm/i915/dmc_wl: Allow enable_dmc_wl=2 to mean
> "match any register"
>
> When debugging issues that might be related to the DMC wakelock code, it is
> sometimes useful to compare runs when we match any register offset vs the
> regular case. If issues disappear when we take the wakelock for any register, it
> might indicate that we are missing some offset to be tracked. Support matching
> any register offset with enable_dmc_wl=2.
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@xxxxxxxxx>
Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@xxxxxxxxx>
Dnyaneshwar
> ---
> .../gpu/drm/i915/display/intel_display_params.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dmc_wl.c | 17 ++++++++++++++---
> 2 files changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c
> b/drivers/gpu/drm/i915/display/intel_display_params.c
> index f92e4640a613..f0f388f38fa7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
> @@ -130,7 +130,7 @@
> intel_display_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400,
>
> intel_display_param_named_unsafe(enable_dmc_wl, int, 0400,
> "Enable DMC wakelock "
> - "(-1=use per-chip default, 0=disabled, 1=enabled) "
> + "(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register) "
> "Default: -1");
>
> __maybe_unused
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> index 2315c6318b51..22e963da65c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> @@ -56,6 +56,7 @@
> enum {
> ENABLE_DMC_WL_DISABLED,
> ENABLE_DMC_WL_ENABLED,
> + ENABLE_DMC_WL_ANY_REGISTER,
> ENABLE_DMC_WL_MAX,
> };
>
> @@ -239,10 +240,15 @@ static bool intel_dmc_wl_reg_in_range(i915_reg_t reg,
> return false;
> }
>
> -static bool intel_dmc_wl_check_range(i915_reg_t reg, u32 dc_state)
> +static bool intel_dmc_wl_check_range(struct intel_display *display,
> + i915_reg_t reg,
> + u32 dc_state)
> {
> const struct intel_dmc_wl_range *ranges;
>
> + if (display->params.enable_dmc_wl ==
> ENABLE_DMC_WL_ANY_REGISTER)
> + return true;
> +
> /*
> * Check that the offset is in one of the ranges for which
> * registers are powered off during DC states.
> @@ -303,6 +309,9 @@ static void intel_dmc_wl_sanitize_param(struct
> intel_display *display)
> case ENABLE_DMC_WL_ENABLED:
> desc = "enabled";
> break;
> + case ENABLE_DMC_WL_ANY_REGISTER:
> + desc = "match any register";
> + break;
> default:
> desc = "unknown";
> break;
> @@ -429,7 +438,8 @@ void intel_dmc_wl_get(struct intel_display *display,
> i915_reg_t reg)
>
> spin_lock_irqsave(&wl->lock, flags);
>
> - if (i915_mmio_reg_valid(reg) && !intel_dmc_wl_check_range(reg, wl-
> >dc_state))
> + if (i915_mmio_reg_valid(reg) &&
> + !intel_dmc_wl_check_range(display, reg, wl->dc_state))
> goto out_unlock;
>
> if (!wl->enabled) {
> @@ -461,7 +471,8 @@ void intel_dmc_wl_put(struct intel_display *display,
> i915_reg_t reg)
>
> spin_lock_irqsave(&wl->lock, flags);
>
> - if (i915_mmio_reg_valid(reg) && !intel_dmc_wl_check_range(reg, wl-
> >dc_state))
> + if (i915_mmio_reg_valid(reg) &&
> + !intel_dmc_wl_check_range(display, reg, wl->dc_state))
> goto out_unlock;
>
> if (WARN_RATELIMIT(!refcount_read(&wl->refcount),
> --
> 2.47.1
