While display initialization along with MBUS credits programming
DBUF_CTL register is also programmed, as a part of it the tracker
state service field is also set to 0x8 value when default value is
other than 0x8 which are for platforms past display version 13.
For remaining platforms the default value is already 0x8 so don't
program them.
Bspec: 49213
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 34465d56def0..98db721cba33 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1126,9 +1126,6 @@ static void gen12_dbuf_slices_config(struct intel_display *display)
{
enum dbuf_slice slice;
- if (display->platform.alderlake_p)
- return;
-
for_each_dbuf_slice(display, slice)
intel_de_rmw(display, DBUF_CTL_S(slice),
DBUF_TRACKER_STATE_SERVICE_MASK,
@@ -1681,7 +1678,7 @@ static void icl_display_core_init(struct intel_display *display,
/* 4. Enable CDCLK. */
intel_cdclk_init_hw(display);
- if (DISPLAY_VER(display) >= 12)
+ if (DISPLAY_VER(display) == 12)
gen12_dbuf_slices_config(display);
/* 5. Enable DBUF. */
--
2.25.1
