While display initialization along with MBUS credits programming
DBUF_CTL register is also programmed, as a part of it the tracker
state service field is also set to 0x8 value when default value is
other than 0x8. so, for TGLLP, SVL, RYF, DG1, ACM, ACMPLUS, RKLC,
RKLGM and ADLS platforms default value is not 0x8, hence set to 0x8.
For remaining platforms the default value is already 0x8 so no need
to program them.
Bspec: 49213
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 34465d56def0..d9ba48b68979 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1126,7 +1126,9 @@ static void gen12_dbuf_slices_config(struct intel_display *display)
{
enum dbuf_slice slice;
- if (display->platform.alderlake_p)
+ if (display->platform.alderlake_p || display->platform.dg2 ||
+ display->platform.alderlake_p_raptorlake_p ||
+ DISPLAY_VER(display) >= 14)
return;
for_each_dbuf_slice(display, slice)
--
2.25.1
