> -----Original Message-----
> From: Govindapillai, Vinod <vinod.govindapillai@xxxxxxxxx>
> Sent: Friday, December 13, 2024 5:34 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; intel-xe@xxxxxxxxxxxxxxxxxxxxx
> Cc: Govindapillai, Vinod <vinod.govindapillai@xxxxxxxxx>; Syrjala, Ville
> <ville.syrjala@xxxxxxxxx>; Shankar, Uma <uma.shankar@xxxxxxxxx>; Saarinen,
> Jani <jani.saarinen@xxxxxxxxx>
> Subject: [PATCH] drm/i915/xe3: do not configure auto min dbuf for cursor WMs
>
> Cursor planes do not have the minimum dbuf confguation. The ddb allocation and
Nit: Typo in configuration.
Change Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx>
> registration routines handle this correctly.
> But the plane wm handling for cursor need to be differentiated for this case. Auto
> minimum buf enable flag should not be enabled for cursor wm registers in xe3.
>
> Fixes: a831920c370c ("drm/i915/xe3: Use hw support for min/interim ddb
> allocations for async flip")
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index d3506e8ccd9b..29e8ea91c858 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -1922,10 +1922,11 @@ static int skl_wm_max_lines(struct
> drm_i915_private *i915)
> return 31;
> }
>
> -static bool xe3_auto_min_alloc_capable(struct intel_display *display,
> - int level)
> +static bool xe3_auto_min_alloc_capable(struct intel_plane *plane, int
> +level)
> {
> - return DISPLAY_VER(display) >= 30 && level == 0;
> + struct intel_display *display = to_intel_display(plane);
> +
> + return DISPLAY_VER(display) >= 30 && level == 0 && plane->id !=
> +PLANE_CURSOR;
> }
>
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> @@ -1937,7 +1938,6 @@ static void skl_compute_plane_wm(const struct
> intel_crtc_state *crtc_state,
> struct skl_wm_level *result /* out */) {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> - struct intel_display *display = to_intel_display(crtc_state);
> uint_fixed_16_16_t method1, method2;
> uint_fixed_16_16_t selected_result;
> u32 blocks, lines, min_ddb_alloc = 0;
> @@ -2061,7 +2061,7 @@ static void skl_compute_plane_wm(const struct
> intel_crtc_state *crtc_state,
> /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here
> */
> result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1;
> result->enable = true;
> - result->auto_min_alloc_wm_enable =
> xe3_auto_min_alloc_capable(display, level);
> + result->auto_min_alloc_wm_enable =
> xe3_auto_min_alloc_capable(plane,
> +level);
>
> if (DISPLAY_VER(i915) < 12 && i915->display.sagv.block_time_us)
> result->can_sagv = latency >= i915->display.sagv.block_time_us;
> --
> 2.34.1
