On Thu, Dec 12, 2024 at 03:10:43PM +0530, Nemesa Garg wrote:
> It was observed that the first write to DKL PHY DP Mode
> register was not taking effect, hence rewrite this register.
>
> v2: Rename function [Mitul]
> v3: Rename function [Jani]
>
> Signed-off-by: Nemesa Garg <nemesa.garg@xxxxxxxxx>
> Signed-off-by: Kulkarni, Vandita <vandita.kulkarni@xxxxxxxxx>
"Last, first" name format with a comma like this causes problems for
git-send-email (it thinks the comma is separating two separate email
addresses and winds up sending a copy of the message to a bogus email
address).
Although that also raises the question what Vandita's s-o-b represents.
If she was involved in the original development of the patch, should
there also be a "Co-developed-by:" line too (as described in
Documentation/process/submitting-patches.rst)?
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4f9c50996446..85b7c30aa9e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2099,10 +2099,21 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
> encoder->disable_clock(encoder);
> }
>
> +static void
> +tgl_dkl_phy_check_and_rewrite(struct drm_i915_private *dev_priv,
> + enum tc_port tc_port, u32 ln0, u32 ln1)
> +{
> + if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
> + intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
> + if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
> + intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
> +}
> +
> static void
> icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
> const struct intel_crtc_state *crtc_state)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
> u32 ln0, ln1, pin_assignment;
> @@ -2180,6 +2191,10 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
> if (DISPLAY_VER(dev_priv) >= 12) {
> intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
> intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
> + /* WA_14018221282 */
> + if (DISPLAY_VER(display) == 12)
The workaround database lists this for both TGL (display version 12) and
ADL-P (display version 13).
At first I was worried that we might be applying this too widely since
it's not listed for other display version 12 platforms (RKL, ADL-S,
DG1), but I see now that won't be a problem since none of those
platforms have MG / DKL PHYs so they'll never descend down to this level
of the code.
So just changing this to "IS_DISPLAY_VER(display, 12, 13)" is probably
sufficient to cover the appropriate platforms (DG2 is also display
version 13, but as with RKL/ADL-S/DG1 it doesn't have MG/DKL PHYs so it
won't see this code anyway).
Matt
> + tgl_dkl_phy_check_and_rewrite(dev_priv, tc_port, ln0, ln1);
> +
> } else {
> intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
> intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
