The register definition is a nightmare to update. Convert to the modern style. Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx> --- drivers/gpu/drm/i915/display/icl_dsi_regs.h | 74 ++++++++++----------- 1 file changed, 34 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi_regs.h b/drivers/gpu/drm/i915/display/icl_dsi_regs.h index 0cb9a5f714d2..88df1da8ccfd 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi_regs.h +++ b/drivers/gpu/drm/i915/display/icl_dsi_regs.h @@ -195,46 +195,40 @@ #define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \ _DSI_TRANS_FUNC_CONF_0,\ _DSI_TRANS_FUNC_CONF_1) -#define OP_MODE_MASK (0x3 << 28) -#define OP_MODE_SHIFT 28 -#define CMD_MODE_NO_GATE (0x0 << 28) -#define CMD_MODE_TE_GATE (0x1 << 28) -#define VIDEO_MODE_SYNC_EVENT (0x2 << 28) -#define VIDEO_MODE_SYNC_PULSE (0x3 << 28) -#define TE_SOURCE_GPIO (1 << 27) -#define LINK_READY (1 << 20) -#define PIX_FMT_MASK (0x7 << 16) -#define PIX_FMT_SHIFT 16 -#define PIX_FMT_RGB565 (0x0 << 16) -#define PIX_FMT_RGB666_PACKED (0x1 << 16) -#define PIX_FMT_RGB666_LOOSE (0x2 << 16) -#define PIX_FMT_RGB888 (0x3 << 16) -#define PIX_FMT_RGB101010 (0x4 << 16) -#define PIX_FMT_RGB121212 (0x5 << 16) -#define PIX_FMT_COMPRESSED (0x6 << 16) -#define BGR_TRANSMISSION (1 << 15) -#define PIX_VIRT_CHAN(x) ((x) << 12) -#define PIX_VIRT_CHAN_MASK (0x3 << 12) -#define PIX_VIRT_CHAN_SHIFT 12 -#define PIX_BUF_THRESHOLD_MASK (0x3 << 10) -#define PIX_BUF_THRESHOLD_SHIFT 10 -#define PIX_BUF_THRESHOLD_1_4 (0x0 << 10) -#define PIX_BUF_THRESHOLD_1_2 (0x1 << 10) -#define PIX_BUF_THRESHOLD_3_4 (0x2 << 10) -#define PIX_BUF_THRESHOLD_FULL (0x3 << 10) -#define CONTINUOUS_CLK_MASK (0x3 << 8) -#define CONTINUOUS_CLK_SHIFT 8 -#define CLK_ENTER_LP_AFTER_DATA (0x0 << 8) -#define CLK_HS_OR_LP (0x2 << 8) -#define CLK_HS_CONTINUOUS (0x3 << 8) -#define LINK_CALIBRATION_MASK (0x3 << 4) -#define LINK_CALIBRATION_SHIFT 4 -#define CALIBRATION_DISABLED (0x0 << 4) -#define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4) -#define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4) -#define BLANKING_PACKET_ENABLE (1 << 2) -#define S3D_ORIENTATION_LANDSCAPE (1 << 1) -#define EOTP_DISABLED (1 << 0) +#define OP_MODE_MASK REG_GENMASK(29, 28) +#define CMD_MODE_NO_GATE REG_FIELD_PREP(OP_MODE_MASK, 0) +#define CMD_MODE_TE_GATE REG_FIELD_PREP(OP_MODE_MASK, 1) +#define VIDEO_MODE_SYNC_EVENT REG_FIELD_PREP(OP_MODE_MASK, 2) +#define VIDEO_MODE_SYNC_PULSE REG_FIELD_PREP(OP_MODE_MASK, 3) +#define TE_SOURCE_GPIO REG_BIT(27) +#define LINK_READY REG_BIT(20) +#define PIX_FMT_MASK REG_GENMASK(18, 16) +#define PIX_FMT_RGB565 REG_FIELD_PREP(PIX_FMT_MASK, 0) +#define PIX_FMT_RGB666_PACKED REG_FIELD_PREP(PIX_FMT_MASK, 1) +#define PIX_FMT_RGB666_LOOSE REG_FIELD_PREP(PIX_FMT_MASK, 2) +#define PIX_FMT_RGB888 REG_FIELD_PREP(PIX_FMT_MASK, 3) +#define PIX_FMT_RGB101010 REG_FIELD_PREP(PIX_FMT_MASK, 4) +#define PIX_FMT_RGB121212 REG_FIELD_PREP(PIX_FMT_MASK, 5) +#define PIX_FMT_COMPRESSED REG_FIELD_PREP(PIX_FMT_MASK, 6) +#define BGR_TRANSMISSION REG_BIT(15) +#define PIX_VIRT_CHAN_MASK REG_GENMASK(13, 12) +#define PIX_VIRT_CHAN(x) REG_FIELD_PREP(PIX_VIRT_CHAN_MASK, (x)) +#define PIX_BUF_THRESHOLD_MASK REG_GENMASK(11, 10) +#define PIX_BUF_THRESHOLD_1_4 REG_FIELD_PREP(PIX_BUF_THRESHOLD_MASK, 0) +#define PIX_BUF_THRESHOLD_1_2 REG_FIELD_PREP(PIX_BUF_THRESHOLD_MASK, 1) +#define PIX_BUF_THRESHOLD_3_4 REG_FIELD_PREP(PIX_BUF_THRESHOLD_MASK, 2) +#define PIX_BUF_THRESHOLD_FULL REG_FIELD_PREP(PIX_BUF_THRESHOLD_MASK, 3) +#define CONTINUOUS_CLK_MASK REG_GENMASK(9, 8) +#define CLK_ENTER_LP_AFTER_DATA REG_FIELD_PREP(CONTINUOUS_CLK_MASK, 0) +#define CLK_HS_OR_LP REG_FIELD_PREP(CONTINUOUS_CLK_MASK, 2) +#define CLK_HS_CONTINUOUS REG_FIELD_PREP(CONTINUOUS_CLK_MASK, 3) +#define LINK_CALIBRATION_MASK REG_GENMASK(5, 4) +#define CALIBRATION_DISABLED REG_FIELD_PREP(LINK_CALIBRATION_MASK, 0) +#define CALIBRATION_ENABLED_INITIAL_ONLY REG_FIELD_PREP(LINK_CALIBRATION_MASK, 2) +#define CALIBRATION_ENABLED_INITIAL_PERIODIC REG_FIELD_PREP(LINK_CALIBRATION_MASK, 3) +#define BLANKING_PACKET_ENABLE REG_BIT(2) +#define S3D_ORIENTATION_LANDSCAPE REG_BIT(1) +#define EOTP_DISABLED REG_BIT(0) #define _DSI_CMD_RXCTL_0 0x6b0d4 #define _DSI_CMD_RXCTL_1 0x6b8d4 -- 2.39.5
