On Wed, 27 Nov 2024, Mika Kahola <mika.kahola@xxxxxxxxx> wrote: > There is a HW issue that arises when there are race conditions > between TCSS entering/exiting TC7 or TC10 states while the > driver is asserting/deasserting TCSS power request. As a > workaround, Display driver will implement a mailbox sequence > to ensure that the TCSS is in TC0 when TCSS power request is > asserted/deasserted. > > The sequence is the following > > 1. Read mailbox command status and wait until run/busy bit is > clear > 2. Write mailbox data value '1' for power request asserting > and '0' for power request deasserting > 3. Write mailbox command run/busy bit and command value with 0x1 > 4. Read mailbox command and wait until run/busy bit is clear > before continuing power request. > > while at it, let's start using struct intel_display instead of > struct drm_i915_private as well. > > Signed-off-by: Mika Kahola <mika.kahola@xxxxxxxxx> Acked-by: Jani Nikula <jani.nikula@xxxxxxxxx> > > Mika Kahola (2): > drm/i915/xe3lpd: Power request asserting/deasserting > drm/i915/display: Use struct intel_display instead of struct > drm_i915_private > > .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 7 ++++ > drivers/gpu/drm/i915/display/intel_tc.c | 39 +++++++++++++++++-- > 2 files changed, 42 insertions(+), 4 deletions(-) -- Jani Nikula, Intel
