From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Split skl_get_plane_caps() into four variants:
skl_plane_caps(), glk_plane_caps(), icl_plane_caps(),
tgl_plane_caps().
Makes it easier to figure out what is actually going on there.
v2: skl_plane_caps() should return u8 not bool
v3: Rebase due to intel_display changes
Reviewed-by: Jouni Högander <jouni.hogander@xxxxxxxxx>
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
.../drm/i915/display/skl_universal_plane.c | 81 +++++++++++++------
1 file changed, 57 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index b06dc106305e..26a44da63352 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2589,48 +2589,74 @@ skl_plane_disable_flip_done(struct intel_plane *plane)
static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
enum pipe pipe, enum plane_id plane_id)
{
- if (DISPLAY_VER(i915) >= 11)
- return true;
-
- if (IS_GEMINILAKE(i915))
- return pipe != PIPE_C;
-
return pipe != PIPE_C &&
(plane_id == PLANE_1 || plane_id == PLANE_2);
}
+static u8 skl_plane_caps(struct drm_i915_private *i915,
+ enum pipe pipe, enum plane_id plane_id)
+{
+ u8 caps = INTEL_PLANE_CAP_TILING_X |
+ INTEL_PLANE_CAP_TILING_Y |
+ INTEL_PLANE_CAP_TILING_Yf;
+
+ if (skl_plane_has_rc_ccs(i915, pipe, plane_id))
+ caps |= INTEL_PLANE_CAP_CCS_RC;
+
+ return caps;
+}
+
+static bool glk_plane_has_rc_ccs(struct drm_i915_private *i915,
+ enum pipe pipe)
+{
+ return pipe != PIPE_C;
+}
+
+static u8 glk_plane_caps(struct drm_i915_private *i915,
+ enum pipe pipe, enum plane_id plane_id)
+{
+ u8 caps = INTEL_PLANE_CAP_TILING_X |
+ INTEL_PLANE_CAP_TILING_Y |
+ INTEL_PLANE_CAP_TILING_Yf;
+
+ if (glk_plane_has_rc_ccs(i915, pipe))
+ caps |= INTEL_PLANE_CAP_CCS_RC;
+
+ return caps;
+}
+
+static u8 icl_plane_caps(struct drm_i915_private *i915,
+ enum pipe pipe, enum plane_id plane_id)
+{
+ return INTEL_PLANE_CAP_TILING_X |
+ INTEL_PLANE_CAP_TILING_Y |
+ INTEL_PLANE_CAP_TILING_Yf |
+ INTEL_PLANE_CAP_CCS_RC;
+}
+
static bool tgl_plane_has_mc_ccs(struct drm_i915_private *i915,
enum plane_id plane_id)
{
- if (DISPLAY_VER(i915) < 12)
- return false;
-
/* Wa_14010477008 */
if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
- (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0)))
+ (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0)))
return false;
return plane_id < PLANE_6;
}
-static u8 skl_get_plane_caps(struct drm_i915_private *i915,
- enum pipe pipe, enum plane_id plane_id)
+static u8 tgl_plane_caps(struct drm_i915_private *i915,
+ enum pipe pipe, enum plane_id plane_id)
{
struct intel_display *display = &i915->display;
- u8 caps = INTEL_PLANE_CAP_TILING_X;
+ u8 caps = INTEL_PLANE_CAP_TILING_X |
+ INTEL_PLANE_CAP_CCS_RC |
+ INTEL_PLANE_CAP_CCS_RC_CC;
- if (DISPLAY_VER(display) < 13 || display->platform.alderlake_p)
- caps |= INTEL_PLANE_CAP_TILING_Y;
- if (DISPLAY_VER(display) < 12)
- caps |= INTEL_PLANE_CAP_TILING_Yf;
if (HAS_4TILE(display))
caps |= INTEL_PLANE_CAP_TILING_4;
-
- if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) {
- caps |= INTEL_PLANE_CAP_CCS_RC;
- if (DISPLAY_VER(display) >= 12)
- caps |= INTEL_PLANE_CAP_CCS_RC_CC;
- }
+ else
+ caps |= INTEL_PLANE_CAP_TILING_Y;
if (tgl_plane_has_mc_ccs(i915, plane_id))
caps |= INTEL_PLANE_CAP_CCS_MC;
@@ -2746,7 +2772,14 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
else
plane_type = DRM_PLANE_TYPE_OVERLAY;
- caps = skl_get_plane_caps(dev_priv, pipe, plane_id);
+ if (DISPLAY_VER(dev_priv) >= 12)
+ caps = tgl_plane_caps(dev_priv, pipe, plane_id);
+ else if (DISPLAY_VER(dev_priv) == 11)
+ caps = icl_plane_caps(dev_priv, pipe, plane_id);
+ else if (DISPLAY_VER(dev_priv) == 10)
+ caps = glk_plane_caps(dev_priv, pipe, plane_id);
+ else
+ caps = skl_plane_caps(dev_priv, pipe, plane_id);
/* FIXME: xe has problems with AUX */
if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(dev_priv))
--
2.45.2
